before enforcing bit def, basck to string

docs/examples/03a_sax_cocotb_cosimulation.py

@@ -54,40 +54,40 @@
 )
 basic_ideal_bits_phase_map.dataframe
 
-# |    |   bits |    phase |
-# |---:|-------:|---------:|
-# |  0 |      0 | 0        |
-# |  1 |      1 | 0.101341 |
-# |  2 |     10 | 0.202681 |
-# |  3 |     11 | 0.304022 |
-# |  4 |    100 | 0.405363 |
-# |  5 |    101 | 0.506703 |
-# |  6 |    110 | 0.608044 |
-# |  7 |    111 | 0.709385 |
-# |  8 |   1000 | 0.810726 |
-# |  9 |   1001 | 0.912066 |
-# | 10 |   1010 | 1.01341  |
-# | 11 |   1011 | 1.11475  |
-# | 12 |   1100 | 1.21609  |
-# | 13 |   1101 | 1.31743  |
-# | 14 |   1110 | 1.41877  |
-# | 15 |   1111 | 1.52011  |
-# | 16 |  10000 | 1.62145  |
-# | 17 |  10001 | 1.72279  |
-# | 18 |  10010 | 1.82413  |
-# | 19 |  10011 | 1.92547  |
-# | 20 |  10100 | 2.02681  |
-# | 21 |  10101 | 2.12815  |
-# | 22 |  10110 | 2.2295   |
-# | 23 |  10111 | 2.33084  |
-# | 24 |  11000 | 2.43218  |
-# | 25 |  11001 | 2.53352  |
-# | 26 |  11010 | 2.63486  |
-# | 27 |  11011 | 2.7362   |
-# | 28 |  11100 | 2.83754  |
-# | 29 |  11101 | 2.93888  |
-# | 30 |  11110 | 3.04022  |
-# | 31 |  11111 | 3.14156  |
+# |    |   bits |    phase   |
+# |----|--------|------------|
+# |  0 |  00000 | 0.000000   |
+# |  1 |  00001 | 0.101341   |
+# |  2 |  00010 | 0.202681   |
+# |  3 |  00011 | 0.304022   |
+# |  4 |  00100 | 0.405363   |
+# |  5 |  00101 | 0.506703   |
+# |  6 |  00110 | 0.608044   |
+# |  7 |  00111 | 0.709385   |
+# |  8 |  01000 | 0.810726   |
+# |  9 |  01001 | 0.912066   |
+# | 10 |  01010 | 1.013410   |
+# | 11 |  01011 | 1.114750   |
+# | 12 |  01100 | 1.216090   |
+# | 13 |  01101 | 1.317430   |
+# | 14 |  01110 | 1.418770   |
+# | 15 |  01111 | 1.520110   |
+# | 16 |  10000 | 1.621450   |
+# | 17 |  10001 | 1.722790   |
+# | 18 |  10010 | 1.824130   |
+# | 19 |  10011 | 1.925470   |
+# | 20 |  10100 | 2.026810   |
+# | 21 |  10101 | 2.128150   |
+# | 22 |  10110 | 2.229500   |
+# | 23 |  10111 | 2.330840   |
+# | 24 |  11000 | 2.432180   |
+# | 25 |  11001 | 2.533520   |
+# | 26 |  11010 | 2.634860   |
+# | 27 |  11011 | 2.736200   |
+# | 28 |  11100 | 2.837540   |
+# | 29 |  11101 | 2.938880   |
+# | 30 |  11110 | 3.040220   |
+# | 31 |  11111 | 3.141560   |
 #
 
 # This allows us to create an operational model of our phase shifter. It is also possible, that if we have a phase-voltage curve, we can also map that to the analog signal, and the analog signal to the DAC converter accordingly, when a Pandas dataframe is provided.
@@ -104,16 +104,19 @@
 cocotb_simulation_output_files = piel.get_simulation_output_files_from_design(
     simple_design
 )
-example_simple_simulation_data = piel.read_simulation_data(
-    cocotb_simulation_output_files[0]
-)
-example_simple_truth_table = piel.types.TruthTable(
+example_simple_truth_table = piel.flows.read_simulation_data_to_truth_table(
+    cocotb_simulation_output_files[0],
     input_ports=["a", "b"],
     output_ports=["x"],
-    **example_simple_simulation_data.to_dict()
 )
 example_simple_truth_table.dataframe
 
+int("0b111", 2)
+
+type(bin(7))
+
+example_simple_truth_table.dataframe.a
+
 # |    |   Unnamed: 0 |    a |    b |     x |     t |
 # |---:|-------------:|-----:|-----:|------:|------:|
 # |  0 |            0 |  101 | 1010 |  1111 |  2001 |

docs/examples/07_full_flow_demo_electronic_photonic/07_full_flow_demo_electronic_photonic.py

@@ -143,6 +143,42 @@ def create_switch_fabric():
 )
 basic_ideal_phase_map.dataframe
 
+# |    |   bits |    phase   |
+# |----|--------|------------|
+# |  0 |  00000 | 0.000000   |
+# |  1 |  00001 | 0.101341   |
+# |  2 |  00010 | 0.202681   |
+# |  3 |  00011 | 0.304022   |
+# |  4 |  00100 | 0.405363   |
+# |  5 |  00101 | 0.506703   |
+# |  6 |  00110 | 0.608044   |
+# |  7 |  00111 | 0.709385   |
+# |  8 |  01000 | 0.810726   |
+# |  9 |  01001 | 0.912066   |
+# | 10 |  01010 | 1.013410   |
+# | 11 |  01011 | 1.114750   |
+# | 12 |  01100 | 1.216090   |
+# | 13 |  01101 | 1.317430   |
+# | 14 |  01110 | 1.418770   |
+# | 15 |  01111 | 1.520110   |
+# | 16 |  10000 | 1.621450   |
+# | 17 |  10001 | 1.722790   |
+# | 18 |  10010 | 1.824130   |
+# | 19 |  10011 | 1.925470   |
+# | 20 |  10100 | 2.026810   |
+# | 21 |  10101 | 2.128150   |
+# | 22 |  10110 | 2.229500   |
+# | 23 |  10111 | 2.330840   |
+# | 24 |  11000 | 2.432180   |
+# | 25 |  11001 | 2.533520   |
+# | 26 |  11010 | 2.634860   |
+# | 27 |  11011 | 2.736200   |
+# | 28 |  11100 | 2.837540   |
+# | 29 |  11101 | 2.938880   |
+# | 30 |  11110 | 3.040220   |
+# | 31 |  11111 | 3.141560   |
+#
+
 truth_table = (
     piel.flows.digital_electro_optic.convert_optical_transitions_to_truth_table(
         optical_state_transitions=chain_fock_state_transitions,

piel/flows/__init__.py

@@ -1,5 +1,6 @@
 from .digital_logic import (
     generate_verilog_and_verification_from_truth_table,
+    read_simulation_data_to_truth_table,
     run_verification_simulation_for_design,
 )
 from .digital_electro_optic import (

piel/flows/digital_logic.py

@@ -5,7 +5,7 @@
     generate_verilog_from_amaranth_truth_table,
     verify_amaranth_truth_table,
 )
-from ..types import PathTypes, TruthTable, HDLSimulator
+from ..types import PathTypes, TruthTable, HDLSimulator, LogicSignalsList, convert_dataframe_to_bytes
 from ..tools.cocotb import (
     configure_cocotb_simulation,
     run_cocotb_simulation,
@@ -76,6 +76,42 @@ def generate_verilog_and_verification_from_truth_table(
     )
 
 
+def read_simulation_data_to_truth_table(
+    file_path: PathTypes,
+    input_ports: LogicSignalsList,
+    output_ports: LogicSignalsList,
+    *args,
+    **kwargs
+) -> TruthTable:
+    """
+    The goal of this function is to read an existing simulation data output from cocotb and convert it into a valid Dataframe with proper type validation of bit signals into the corresponding byte formats.
+
+    Args:
+    - file_path (PathTypes): The path to the simulation data file.
+    - input_ports (LogicSignalsList): The list of input port names.
+    - output_ports (LogicSignalsList): The list of output port names.
+
+    Returns:
+    - truth_table (TruthTable): The truth table object containing the input and output port data.
+
+    Examples:
+    >>> read_simulation_data_to_truth_table("simulation_data.csv", ["input_port"], ["output_port"])
+    TruthTable(input_ports=["input_port"], output_ports=["output_port"], ...)
+    """
+    # Combine input and output ports into a single list for ports
+    ports_list = input_ports + output_ports
+    # Read the simulation data from the file
+    simulation_dataframe = read_simulation_data(file_path, *args, **kwargs)
+    # Convert the integer columns to byte format
+    simulation_dataframe = convert_dataframe_to_bytes(dataframe=simulation_dataframe, ports_list=ports_list)
+    # Create a TruthTable object from the simulation data
+    truth_table = TruthTable(
+        input_ports=input_ports,
+        output_ports=output_ports,
+        **simulation_dataframe.to_dict()
+    )
+    return truth_table
+
 def run_verification_simulation_for_design(
     module: PathTypes,
     top_level_verilog_module: str,

piel/models/logic/electro_optic/signal_map.py

@@ -21,15 +21,13 @@
 import numpy as np
 from ..electronic.digital import bits_array_from_bits_amount
 from ....types.digital_electro_optic import BitPhaseMap
-from ....types.digital import AbstractBitsType
 
 
 def linear_bit_phase_map(
     bits_amount: int,
     final_phase_rad: float,
     initial_phase_rad: float = 0,
     quantization_error: float = 0.000001,
-    bit_format: AbstractBitsType = int,
 ) -> BitPhaseMap:
     """
     Returns a linear direct mapping of bits to phase.
@@ -39,29 +37,31 @@ def linear_bit_phase_map(
         final_phase_rad(float): Final phase to map to.
         initial_phase_rad(float): Initial phase to map to.
         quantization_error(float): Error in the phase mapping.
-        bit_format(Literal["int", "str"]): Format of the bits.
-
 
     Returns:
-        bit_phase_mapping(dict): Mapping of bits to phase.
+        BitPhaseMap: Mapping of bits to phase.
     """
+    # Generate the binary combinations for the specified bit amount
     bits_array = bits_array_from_bits_amount(bits_amount)
+
+    # Calculate the number of divisions in the phase space
     phase_division_amount = len(bits_array) - 1
+
+    # Calculate the step size for each phase division, adjusting for quantization error
     phase_division_step = (
                               final_phase_rad - initial_phase_rad
                           ) / phase_division_amount - quantization_error
+
+    # Generate the phase array using numpy's arange
     linear_phase_array = np.arange(
         initial_phase_rad, final_phase_rad, phase_division_step
     )
 
-    if bit_format == int:
-        pass
-    elif bit_format == str:
-        bits_array = bits_array_from_bits_amount(bits_amount, bit_format=bit_format)
+    # Ensure that we have enough phases for all bits; handle edge cases where rounding might cause fewer steps
+    if len(linear_phase_array) < len(bits_array):
+        linear_phase_array = np.append(linear_phase_array, final_phase_rad)
+
+    # Create the BitPhaseMap object
+    bit_phase_mapping = BitPhaseMap(bits=bits_array, phase=linear_phase_array)
 
-    bit_phase_mapping_raw = {
-        "bits": bits_array,
-        "phase": linear_phase_array,
-    }
-    bit_phase_mapping = BitPhaseMap(**bit_phase_mapping_raw)
     return bit_phase_mapping

piel/models/logic/electronic/digital.py

@@ -1,27 +1,23 @@
-import numpy as np
-from ....types import BitsList, AbstractBitsType
+from ....types import BitsList
 
 
-def bits_array_from_bits_amount(
-    bits_amount: int,
-    bit_format: AbstractBitsType = "int",
-) -> BitsList:
+def bits_array_from_bits_amount(bits_amount: int) -> BitsList:
     """
-    Returns an array of bits from a given amount of bits.
+    Returns an array of bits (in bytes) of a given length.
 
     Args:
         bits_amount(int): Amount of bits to generate.
-        bit_format(str): Format of the bits to generate.
 
     Returns:
-        bit_array(np.ndarray): Array of bits.
+        BitsList: List of binary representations in bytes.
     """
-    maximum_integer_represented = 2 ** (bits_amount)
-    int_array = np.arange(maximum_integer_represented)
-    bit_array = np.vectorize(np.base_repr)(int_array)
-    if bit_format == "int":
-        pass
-    elif bit_format == "str":
-        # Add leading zeros to bit strings
-        bit_array = np.vectorize(lambda x: x.zfill(bits_amount))(bit_array)
+    # Generate range of integers from 0 to 2^bits_amount - 1
+    maximum_integer_represented = 2 ** bits_amount
+
+    # Convert each integer to its binary representation, padded with leading zeros
+    bit_array = [
+        format(i, f'0{bits_amount}b').encode('ascii')  # Convert each binary string to bytes
+        for i in range(maximum_integer_represented)
+    ]
+
     return bit_array

piel/tools/cocotb/data.py

@@ -40,7 +40,11 @@ def get_simulation_output_files_from_design(
     return output_files
 
 
-def read_simulation_data(file_path: PathTypes) -> pd.DataFrame:
+def read_simulation_data(
+    file_path: PathTypes,
+    *args,
+    **kwargs
+) -> pd.DataFrame:
     """
     Reads simulation data from a specified file into a Pandas dataframe.
 
@@ -55,7 +59,7 @@ def read_simulation_data(file_path: PathTypes) -> pd.DataFrame:
         # Returns a dataframe with the contents of the CSV file.
     """
     file_path = return_path(file_path)
-    simulation_data = pd.read_csv(file_path)
+    simulation_data = pd.read_csv(file_path, dtype=str, encoding='utf-8', *args, **kwargs)
     return simulation_data
 
 

piel/types/__init__.py

@@ -54,4 +54,5 @@
     convert_tuple_to_string,
     convert_2d_array_to_string,
     convert_to_bits,
+    convert_dataframe_to_bytes
 )

piel/types/digital.py

@@ -9,7 +9,7 @@
 from .core import PielBaseModel
 
 # Type aliases for different types of digital bits and HDL simulators.
-AbstractBitsType = str | bytes | int | bin
+AbstractBitsType = str | bytes | int
 """
 AbstractBitsType: Alias for types representing digital bits.
     Can be one of:
@@ -18,13 +18,13 @@
     - int: An integer representation of bits.
 """
 
-BitsType = bin
+BitsType = bytes
 """
 BitsType: A type representing binary digital bits.
-    It is an alias for the 'bin' type.
+    It is an alias for the 'bytes' type.
 """
 
-BitsList = Iterable[AbstractBitsType]
+BitsList = Iterable[BitsType]
 """
 BitsList: An iterable collection of AbstractBitsType elements.
     Represents a sequence of digital bits.

piel/types/digital_electro_optic.py

@@ -6,7 +6,7 @@
 import numpy as np
 import pandas as pd
 from .core import NumericalTypes, PielBaseModel
-from .digital import AbstractBitsType
+from .digital import BitsType
 
 
 class BitPhaseMap(PielBaseModel):
@@ -24,7 +24,7 @@ class BitPhaseMap(PielBaseModel):
             A pandas DataFrame representation of the BitPhaseMap, combining the bits and phases into a tabular format.
     """
 
-    bits: list[AbstractBitsType] | tuple[AbstractBitsType] | np.ndarray
+    bits: list[BitsType] | tuple[BitsType] | np.ndarray
     """
     bits (list[AbstractBitsType] | tuple[AbstractBitsType] | np.ndarray):
         An iterable collection of bits.