dirty implementation complete

docs/examples/03a_sax_cocotb_cosimulation.py

@@ -126,7 +126,7 @@
 # We can get the phase that is mapped to this electronic data accordingly:
 
 basic_ideal_phase_array = (
-    piel.models.logic.electro_optic.return_phase_array_from_data_series(
+    piel.flows.digital_electro_optic.return_phase_array_from_data_series(
         data_series=example_simple_simulation_data.x, phase_map=basic_ideal_phase_map
     )
 )

docs/examples/10_demo_full_flow/10_demo_full_flow.py

@@ -125,15 +125,49 @@ def create_switch_fabric():
     mode_amount=3,
     target_mode_index=2,
 )
-pd.DataFrame(chain_fock_state_transmission_list)
-# CURRENT TODO Fix this so that it actually maps the phase accordingly.
-# Here we want a truth table that shows the phase mapping to the corresponding changes of the fock states accordingly.
+raw_optical_transmission_table = pd.DataFrame(chain_fock_state_transmission_list)
 
+# Now, we actually need to get the required electronic logic we want to implement, and map it back to a given binary implementation, into a corresponding truth table accordingly.
+#
+# Let's start by extracting our desired optical logic implementation:
 
+target_implementation_optical_logic_table = raw_optical_transmission_table[
+    raw_optical_transmission_table["target_mode_output"] == 1
+].copy()
+target_implementation_optical_logic_table
 
-pd.DataFrame(chain_fock_state_transmission_list[2]).T
+# Now, each of these electronic phases applied correspond to a given digital value that we want to impelment on the electronic logic.
 
-# Now, we actually need to get the required electronic logic we want to implement, and map it back to a given binary implementation, into a corresponding truth table accordingly.
+basic_ideal_phase_map = piel.models.logic.electro_optic.linear_bit_phase_map(
+    bits_amount=5, final_phase_rad=np.pi, initial_phase_rad=0
+)
+basic_ideal_phase_map
+
+target_implementation_optical_logic_table[
+    "phase_bit"
+] = piel.flows.digital_electro_optic.convert_dataframe_to_bit_tuple(
+    dataframe=target_implementation_optical_logic_table,
+    phase_column_name="phase",
+    phase_bit_dataframe=basic_ideal_phase_map,
+    phase_series_name="phase",
+    bit_series_name="bits",
+)
+target_implementation_optical_logic_table
+
+# +
+input_ports_list = ["input_fock_state"]
+output_ports_list = ["phase_bit"]
+
+
+target_truth_table = (
+    piel.flows.digital_electro_optic.convert_dataframe_to_truth_table_dictionary(
+        truth_table_dataframe=target_implementation_optical_logic_table,
+        input_ports=input_ports_list,
+        output_ports=output_ports_list,
+    )
+)
+target_truth_table
+# -
 
 # ## 3. Synthesizing the logic, digtial testing and layout implementation
 
@@ -142,17 +176,10 @@ def create_switch_fabric():
 # Inputs truth table, input port list, output port list, module
 # No outputs
 
-detector_phase_truth_table = {
-    "detector_in": ["00", "01", "10", "11"],
-    "phase_map_out": ["00", "10", "11", "11"],
-}
-
 # Define all the relevant ports from the dictionary
-input_ports_list = ["detector_in"]
-output_ports_list = ["phase_map_out"]
 
 piel.flows.generate_verilog_and_verification_from_truth_table(
-    truth_table=detector_phase_truth_table,
+    truth_table=target_truth_table,
     input_ports=input_ports_list,
     output_ports=output_ports_list,
     module=full_flow_demo,
@@ -182,7 +209,7 @@ def create_switch_fabric():
 
 piel.integration.create_cocotb_truth_table_verification_python_script(
     module=full_flow_demo,
-    truth_table=detector_phase_truth_table,
+    truth_table=target_truth_table,
     test_python_module_name="test_top",
 )
 
@@ -424,7 +451,7 @@ def compute_simulation_unitaries(
     inputs_name_list=input_ports_list,
     outputs_name_list=output_ports_list,
     parent_directory=amaranth_driven_flow,
-    openlane_version="v1",
+    openlane_version="v2",
 )
 
 # ## 4a. Driver-Amplfier Modelling

docs/examples/10_demo_full_flow/full_flow_demo/full_flow_demo/src/truth_table_module.v

@@ -2,31 +2,31 @@
 
 (* top =  1  *)
 (* generator = "Amaranth" *)
-module top(phase_map_out, detector_in);
+module top(phase_bit, input_fock_state);
   reg \$auto$verilog_backend.cc:2352:dump_module$1  = 0;
   (* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:48" *)
-  input [1:0] detector_in;
-  wire [1:0] detector_in;
+  input [2:0] input_fock_state;
+  wire [2:0] input_fock_state;
   (* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:48" *)
-  output [1:0] phase_map_out;
-  reg [1:0] phase_map_out;
+  output [9:0] phase_bit;
+  reg [9:0] phase_bit;
   always @* begin
     if (\$auto$verilog_backend.cc:2352:dump_module$1 ) begin end
     (* full_case = 32'd1 *)
     (* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:62" *)
-    casez (detector_in)
+    casez (input_fock_state)
       /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:65" */
-      2'h0:
-          phase_map_out = 2'h0;
+      3'h4:
+          phase_bit = 10'h000;
       /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:65" */
-      2'h1:
-          phase_map_out = 2'h2;
+      3'h1:
+          phase_bit = 10'h3e0;
       /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:65" */
-      2'h2:
-          phase_map_out = 2'h3;
-      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:65" */
-      2'h3:
-          phase_map_out = 2'h3;
+      3'h2:
+          phase_bit = 10'h01f;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:69" */
+      default:
+          phase_bit = 10'h000;
     endcase
   end
 endmodule

docs/examples/10_demo_full_flow/full_flow_demo/full_flow_demo/tb/out/truth_table_test_results.csv

@@ -1,5 +1,5 @@
-,detector_in,phase_map_out,time
-0,00,00,2000
-1,01,10,4000
-2,10,11,6000
-3,11,11,8000
+,input_fock_state,phase_bit,time
+0,100,0000000000,2000
+1,001,1111100000,4000
+2,010,0000011111,6000
+3,001,1111100000,8000

docs/examples/10_demo_full_flow/full_flow_demo/full_flow_demo/tb/test_top.py

@@ -1,59 +1,69 @@
-
 # This file is public domain, it can be freely copied without restrictions.
 # SPDX-License-Identifier: CC0-1.0
 import cocotb
 from cocotb.triggers import Timer
 from cocotb.utils import get_sim_time
 import pandas as pd
 
+
 @cocotb.test()
 async def truth_table_test(dut):
     """Test for logic defined by the truth table"""
 
-    detector_in_data = []
-    phase_map_out_data = []
+    input_fock_state_data = []
+    phase_bit_data = []
     time_data = []
 
     # Test case 1
-    dut.detector_in.value = cocotb.binary.BinaryValue("00")
-    await Timer(2, units='ns')
+    dut.input_fock_state.value = cocotb.binary.BinaryValue("100")
+    await Timer(2, units="ns")
 
-    assert dut.phase_map_out.value == cocotb.binary.BinaryValue("00"), f"Test failed for inputs ['detector_in']: expected 00 but got {dut.phase_map_out.value}."
-    detector_in_data.append(dut.detector_in.value)
-    phase_map_out_data.append(dut.phase_map_out.value)
+    assert dut.phase_bit.value == cocotb.binary.BinaryValue(
+        "0000000000"
+    ), f"Test failed for inputs ['input_fock_state']: expected 0000000000 but got {dut.phase_bit.value}."
+    input_fock_state_data.append(dut.input_fock_state.value)
+    phase_bit_data.append(dut.phase_bit.value)
     time_data.append(get_sim_time())
 
     # Test case 2
-    dut.detector_in.value = cocotb.binary.BinaryValue("01")
-    await Timer(2, units='ns')
+    dut.input_fock_state.value = cocotb.binary.BinaryValue("001")
+    await Timer(2, units="ns")
 
-    assert dut.phase_map_out.value == cocotb.binary.BinaryValue("10"), f"Test failed for inputs ['detector_in']: expected 10 but got {dut.phase_map_out.value}."
-    detector_in_data.append(dut.detector_in.value)
-    phase_map_out_data.append(dut.phase_map_out.value)
+    assert dut.phase_bit.value == cocotb.binary.BinaryValue(
+        "1111100000"
+    ), f"Test failed for inputs ['input_fock_state']: expected 1111100000 but got {dut.phase_bit.value}."
+    input_fock_state_data.append(dut.input_fock_state.value)
+    phase_bit_data.append(dut.phase_bit.value)
     time_data.append(get_sim_time())
 
     # Test case 3
-    dut.detector_in.value = cocotb.binary.BinaryValue("10")
-    await Timer(2, units='ns')
+    dut.input_fock_state.value = cocotb.binary.BinaryValue("010")
+    await Timer(2, units="ns")
 
-    assert dut.phase_map_out.value == cocotb.binary.BinaryValue("11"), f"Test failed for inputs ['detector_in']: expected 11 but got {dut.phase_map_out.value}."
-    detector_in_data.append(dut.detector_in.value)
-    phase_map_out_data.append(dut.phase_map_out.value)
+    assert dut.phase_bit.value == cocotb.binary.BinaryValue(
+        "0000011111"
+    ), f"Test failed for inputs ['input_fock_state']: expected 0000011111 but got {dut.phase_bit.value}."
+    input_fock_state_data.append(dut.input_fock_state.value)
+    phase_bit_data.append(dut.phase_bit.value)
     time_data.append(get_sim_time())
 
     # Test case 4
-    dut.detector_in.value = cocotb.binary.BinaryValue("11")
-    await Timer(2, units='ns')
+    dut.input_fock_state.value = cocotb.binary.BinaryValue("001")
+    await Timer(2, units="ns")
 
-    assert dut.phase_map_out.value == cocotb.binary.BinaryValue("11"), f"Test failed for inputs ['detector_in']: expected 11 but got {dut.phase_map_out.value}."
-    detector_in_data.append(dut.detector_in.value)
-    phase_map_out_data.append(dut.phase_map_out.value)
+    assert dut.phase_bit.value == cocotb.binary.BinaryValue(
+        "1111100000"
+    ), f"Test failed for inputs ['input_fock_state']: expected 1111100000 but got {dut.phase_bit.value}."
+    input_fock_state_data.append(dut.input_fock_state.value)
+    phase_bit_data.append(dut.phase_bit.value)
     time_data.append(get_sim_time())
 
     simulation_data = {
-        "detector_in": detector_in_data,
-        "phase_map_out": phase_map_out_data,
-        "time": time_data
+        "input_fock_state": input_fock_state_data,
+        "phase_bit": phase_bit_data,
+        "time": time_data,
     }
 
-    pd.DataFrame(simulation_data).to_csv("/home/daquintero/phd/piel_private/docs/examples/10_demo_full_flow/full_flow_demo/full_flow_demo/tb/out/truth_table_test_results.csv") 
+    pd.DataFrame(simulation_data).to_csv(
+        "/home/daquintero/phd/piel_private/docs/examples/10_demo_full_flow/full_flow_demo/full_flow_demo/tb/out/truth_table_test_results.csv"
+    )

piel/flows/__init__.py

@@ -2,7 +2,9 @@
     generate_verilog_and_verification_from_truth_table,
     run_verification_simulation_for_design,
 )
-from .digital_to_electro_optic import (
+from .digital_electro_optic import (
+    convert_dataframe_to_truth_table_dictionary,
+    convert_dataframe_to_bit_tuple,
     convert_phase_array_to_bit_array,
     find_nearest_bit_for_phase,
     return_phase_array_from_data_series,