📚 Continued improving presentation

daquintero · Jun 21, 2024 · 4dda06d · 4dda06d
1 parent 29bca45
commit 4dda06d
Show file tree

Hide file tree

Showing 852 changed files with 7,417 additions and 440,857 deletions.
diff --git a/...atic/img/examples/03a_sax_active_cosimulation/simple_ideal_o3_mzi_2x2_plots.PNG b/...atic/img/examples/03a_sax_active_cosimulation/simple_ideal_o3_mzi_2x2_plots.PNG
diff --git a/...atic/img/examples/03a_sax_active_cosimulation/simple_ideal_o4_mzi_2x2_plots.PNG b/...atic/img/examples/03a_sax_active_cosimulation/simple_ideal_o4_mzi_2x2_plots.PNG
diff --git a/docs/_static/img/examples/04_spice_cosimulation/linear_phase_power_mapping.png b/docs/_static/img/examples/04_spice_cosimulation/linear_phase_power_mapping.png
diff --git a/docs/_static/img/examples/04_spice_cosimulation/simple_ideal_o3_mzi_2x2_plots.PNG b/docs/_static/img/examples/04_spice_cosimulation/simple_ideal_o3_mzi_2x2_plots.PNG
diff --git a/docs/_static/img/examples/04_spice_cosimulation/simple_ideal_o4_mzi_2x2_plots.PNG b/docs/_static/img/examples/04_spice_cosimulation/simple_ideal_o4_mzi_2x2_plots.PNG
diff --git a/docs/_static/img/examples/04_spice_cosimulation/simple_transient_plot.PNG b/docs/_static/img/examples/04_spice_cosimulation/simple_transient_plot.PNG
diff --git a/docs/_static/img/examples/04_spice_cosimulation/simple_transient_plot_full.PNG b/docs/_static/img/examples/04_spice_cosimulation/simple_transient_plot_full.PNG
diff --git a/...c/img/examples/04_spice_cosimulation/simple_transient_plot_power_resistance.PNG b/...c/img/examples/04_spice_cosimulation/simple_transient_plot_power_resistance.PNG
diff --git a/..._static/img/examples/07_full_flow_demo_electronic_photonic/demo_design_flow.png b/..._static/img/examples/07_full_flow_demo_electronic_photonic/demo_design_flow.png
diff --git a/docs/_static/img/examples/07_full_flow_demo_electronic_photonic/demo_schematic.png b/docs/_static/img/examples/07_full_flow_demo_electronic_photonic/demo_schematic.png
diff --git a/...img/examples/07_full_flow_demo_electronic_photonic/example_gtk_wave_signals.png b/...img/examples/07_full_flow_demo_electronic_photonic/example_gtk_wave_signals.png
diff --git a/docs/_static/resources/fsic_2024_presentation.odp b/docs/_static/resources/fsic_2024_presentation.odp
diff --git a/docs/examples/01_run_openlane_flow.py b/docs/examples/01_run_openlane_flow.py
diff --git a/docs/examples/02_digital_design_simulation/02_digital_design_simulation.py b/docs/examples/02_digital_design_simulation/02_digital_design_simulation.py
@@ -7,6 +7,7 @@
 # * `cocotb` is mainly used for writing testbenches in Python and verification of logic.
 
 import piel
+from piel.types import TruthTable
 
 import simple_design
 
@@ -19,19 +20,16 @@
     verify_amaranth_truth_table,
 )
 
-# +
-# Uncomment this if you want to run it for the first time.
-# piel.create_empty_piel_project(
-#     project_name="amaranth_driven_flow", parent_directory="../designs/"
-# )
-# -
+# # Uncomment this if you want to run it for the first time.
+piel.create_empty_piel_project(
+    project_name="amaranth_driven_flow", parent_directory="../designs/"
+)
 
 # We can also automate the `pip` installation of our local module:
 
-# +
+# ! pip install -e ../designs/amaranth_driven_flow
 #  Uncomment this if you want to run it for the first time.
 # piel.pip_install_local_module("../designs/amaranth_driven_flow")
-# -
 
 # We can check that this has been installed. You might need to restart your `jupyter` kernel.
 
@@ -64,15 +62,15 @@
     "detector_in": ["00", "01", "10", "11"],
     "phase_map_out": ["00", "10", "11", "11"],
 }
-detector_phase_truth_table = piel.types.TruthTable(
+detector_phase_truth_table = TruthTable(
     input_ports=["detector_in"],
     output_ports=["phase_map_out"],
     **detector_phase_truth_table_dictionary
 )
 
 
 our_truth_table_module = construct_amaranth_module_from_truth_table(
-    truth_table=detector_phase_truth_table,
+    truth_table=detector_phase_truth_table
 )
 
 # `amaranth` is much easier to use than other design flows like `cocotb` because it can be purely interacted with in `Python`, which means there are fewer complexities of integration. However, if you desire to use this with other digital layout tools, for example, `OpenROAD` as we have previously seen and maintain a coherent project structure with the photonics design flow, `piel` provides some helper functions to achieve this easily.
@@ -82,7 +80,7 @@
 generate_verilog_from_amaranth_truth_table(
     amaranth_module=our_truth_table_module,
     truth_table=detector_phase_truth_table,
-    target_file_name="our_truth_table_module.v",
+    target_file_name="truth_table_module.v",
     target_directory=".",
 )
 
@@ -105,38 +103,38 @@
 generate_verilog_from_amaranth_truth_table(
     amaranth_module=our_truth_table_module,
     truth_table=detector_phase_truth_table,
-    target_file_name="our_truth_table_module.v",
+    target_file_name="truth_table_module.v",
     target_directory=amaranth_driven_flow_src_folder,
 )
 
 # ```
-# Verilog file generated and written to /home/daquintero/phd/piel/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/src/our_truth_table_module.v
+# Verilog file generated and written to /home/daquintero/phd/piel/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/src/truth_table_module.v
 # ```
 
 # Another thing we can do is verify that our implemented logic is valid. Creating a simulation is also useful in the future when we simulate our extracted place-and-route netlist in relation to the expected applied logic.
 
 verify_amaranth_truth_table(
     truth_table_amaranth_module=our_truth_table_module,
     truth_table=detector_phase_truth_table,
-    vcd_file_name="our_truth_table_module.vcd",
+    vcd_file_name="truth_table_module.vcd",
     target_directory=".",
 )
 
 # ```
-# VCD file generated and written to /home/daquintero/phd/piel/docs/examples/02_digital_design_simulation/our_truth_table_module.vcd
+# VCD file generated and written to /home/daquintero/phd/piel/docs/examples/02_digital_design_simulation/truth_table_module.vcd
 # ```
 
 # You can also use the module directory to automatically save the testbench in these functions.
 
 verify_amaranth_truth_table(
     truth_table_amaranth_module=our_truth_table_module,
     truth_table=detector_phase_truth_table,
-    vcd_file_name="our_truth_table_module.vcd",
+    vcd_file_name="truth_table_module.vcd",
     target_directory=amaranth_driven_flow,
 )
 
 # ```
-# VCD file generated and written to /home/daquintero/phd/piel/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/tb/our_truth_table_module.vcd
+# VCD file generated and written to /home/daquintero/phd/piel/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/tb/truth_table_module.vcd
 # ```
 
 # You can observe the design directory of the provided `amaranth_driven_flow` folder to verify that the files have been included in the other flow.
@@ -158,7 +156,36 @@
     amaranth_module=our_truth_table_module,
     truth_table=detector_phase_truth_table,
     parent_directory=amaranth_driven_flow,
-    openlane_version="v1",
+    openlane_version="v2",
+)
+
+# +
+from piel.types import TruthTable
+import piel
+
+detector_phase_truth_table = {
+    "detector_in": ["00", "01", "10", "11"],
+    "phase_map_out": ["00", "10", "11", "11"],
+}
+truth_table = TruthTable(
+    input_ports=["detector_in"],
+    output_ports=["phase_map_out"],
+    **detector_phase_truth_table
+)
+am_module = piel.amaranth.construct_amaranth_module_from_truth_table(
+    truth_table, logic_implementation_type="sequential"
+)
+am_module
+
+from piel.integration.amaranth_openlane import (
+    layout_amaranth_truth_table_through_openlane,
+)
+
+layout_amaranth_truth_table_through_openlane(
+    amaranth_module=am_module,
+    truth_table=truth_table,
+    parent_directory="openlane_run",
+    openlane_version="v2",
 )
 # -
 
@@ -319,3 +346,42 @@
 # This looks like this:
 
 # ![example_simple_design_outputs](../../_static/img/examples/02_cocotb_simulation/example_simple_design_outputs.PNG)
+
+# ## Sequential Implementation
+
+# +
+from openlane.flows import SequentialFlow
+from openlane.steps import Yosys, Misc, OpenROAD, Magic, Netgen
+
+
+class MyFlow(SequentialFlow):
+    Steps = [
+        Yosys.Synthesis,
+        OpenROAD.Floorplan,
+        OpenROAD.TapEndcapInsertion,
+        OpenROAD.GeneratePDN,
+        OpenROAD.IOPlacement,
+        OpenROAD.GlobalPlacement,
+        OpenROAD.DetailedPlacement,
+        OpenROAD.GlobalRouting,
+        OpenROAD.DetailedRouting,
+        OpenROAD.FillInsertion,
+        Magic.StreamOut,
+        Magic.DRC,
+        Magic.SpiceExtraction,
+        Netgen.LVS,
+    ]
+
+
+flow = MyFlow(
+    {
+        "PDK": "sky130A",
+        "DESIGN_NAME": "spm",
+        "VERILOG_FILES": ["./src/spm.v"],
+        "CLOCK_PORT": "clk",
+        "CLOCK_PERIOD": 10,
+    },
+    design_dir=".",
+)
+flow.start()
+# -
diff --git a/...9-openroad-globalrouting/antenna_nets.txt → ...hTableModule/TruthTableModule/__init__.py b/...9-openroad-globalrouting/antenna_nets.txt → ...hTableModule/TruthTableModule/__init__.py
diff --git a/...17-18/32-openroad-detailedrouting/top.drc → ...ule/TruthTableModule/analogue/__init__.py b/...17-18/32-openroad-detailedrouting/top.drc → ...ule/TruthTableModule/analogue/__init__.py
diff --git a/...-17-18/40-openroad-stapostpnr/summary.rpt → ...e/TruthTableModule/components/__init__.py b/...-17-18/40-openroad-stapostpnr/summary.rpt → ...e/TruthTableModule/components/__init__.py
diff --git a/...w/runs/RUN_2023-09-06_14-17-18/errors.log → ...bleModule/components/analogue/__init__.py b/...w/runs/RUN_2023-09-06_14-17-18/errors.log → ...bleModule/components/analogue/__init__.py
diff --git a/...runs/RUN_2023-09-06_14-17-18/warnings.log → ...ableModule/components/digital/__init__.py b/...runs/RUN_2023-09-06_14-17-18/warnings.log → ...ableModule/components/digital/__init__.py
diff --git a/...23.08.22_00.06.09/reports/routing/drt.drc → ...leModule/components/photonics/__init__.py b/...23.08.22_00.06.09/reports/routing/drt.drc → ...leModule/components/photonics/__init__.py
diff --git a/.../reports/signoff/38-antenna_violators.rpt → ...odule/TruthTableModule/models/__init__.py b/.../reports/signoff/38-antenna_violators.rpt → ...odule/TruthTableModule/models/__init__.py
diff --git a/...23.08.22_00.06.09/reports/signoff/drc.tcl → ...thTableModule/models/analogue/__init__.py b/...23.08.22_00.06.09/reports/signoff/drc.tcl → ...thTableModule/models/analogue/__init__.py
diff --git a/...023.08.22_00.06.09/reports/signoff/drc.tr → ...hTableModule/models/frequency/__init__.py b/...023.08.22_00.06.09/reports/signoff/drc.tr → ...hTableModule/models/frequency/__init__.py
diff --git a/...design_simulation/openlane_run/TruthTableModule/TruthTableModule/models/logic/__init__.py b/...design_simulation/openlane_run/TruthTableModule/TruthTableModule/models/logic/__init__.py
diff --git a/...ign_simulation/openlane_run/TruthTableModule/TruthTableModule/models/physical/__init__.py b/...ign_simulation/openlane_run/TruthTableModule/TruthTableModule/models/physical/__init__.py
diff --git a/...gn_simulation/openlane_run/TruthTableModule/TruthTableModule/models/transient/__init__.py b/...gn_simulation/openlane_run/TruthTableModule/TruthTableModule/models/transient/__init__.py
diff --git a/...tal_design_simulation/openlane_run/TruthTableModule/TruthTableModule/photonic/__init__.py b/...tal_design_simulation/openlane_run/TruthTableModule/TruthTableModule/photonic/__init__.py
diff --git a/...design_simulation/openlane_run/TruthTableModule/TruthTableModule/src/truth_table_module.v b/...design_simulation/openlane_run/TruthTableModule/TruthTableModule/src/truth_table_module.v
@@ -0,0 +1,89 @@
+/* Generated by Yosys 0.38 (git sha1 543faed9c8c, clang++ 17.0.6 -fPIC -Os) */
+
+(* top =  1  *)
+(* generator = "Amaranth" *)
+module top(phase_map_out, clk, rst, detector_in);
+  reg \$auto$verilog_backend.cc:2334:dump_module$1  = 0;
+  (* src = "/home/daquintero/.pyenv/versions/3.10.13/envs/piel_0_57/lib/python3.10/site-packages/amaranth/hdl/ir.py:508" *)
+  input clk;
+  wire clk;
+  (* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:139" *)
+  input [1:0] detector_in;
+  wire [1:0] detector_in;
+  (* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:160" *)
+  reg [1:0] next_state = 2'h0;
+  (* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:160" *)
+  reg [1:0] \next_state$next ;
+  (* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:141" *)
+  output [1:0] phase_map_out;
+  reg [1:0] phase_map_out = 2'h0;
+  (* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:141" *)
+  reg [1:0] \phase_map_out$next ;
+  (* src = "/home/daquintero/.pyenv/versions/3.10.13/envs/piel_0_57/lib/python3.10/site-packages/amaranth/hdl/ir.py:508" *)
+  input rst;
+  wire rst;
+  (* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:154" *)
+  reg [1:0] state = 2'h0;
+  (* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:154" *)
+  reg [1:0] \state$next ;
+  always @(posedge clk)
+    state <= \state$next ;
+  always @(posedge clk)
+    next_state <= \next_state$next ;
+  always @(posedge clk)
+    phase_map_out <= \phase_map_out$next ;
+  always @* begin
+    if (\$auto$verilog_backend.cc:2334:dump_module$1 ) begin end
+    \state$next  = next_state;
+    (* src = "/home/daquintero/.pyenv/versions/3.10.13/envs/piel_0_57/lib/python3.10/site-packages/amaranth/hdl/xfrm.py:503" *)
+    if (rst) begin
+      \state$next  = 2'h0;
+    end
+  end
+  always @* begin
+    if (\$auto$verilog_backend.cc:2334:dump_module$1 ) begin end
+    (* full_case = 32'd1 *)
+    (* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:165" *)
+    casez (detector_in)
+      /* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:168" */
+      2'h0:
+          \next_state$next  = 2'h0;
+      /* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:168" */
+      2'h1:
+          \next_state$next  = 2'h1;
+      /* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:168" */
+      2'h2:
+          \next_state$next  = 2'h2;
+      /* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:168" */
+      2'h3:
+          \next_state$next  = 2'h3;
+    endcase
+    (* src = "/home/daquintero/.pyenv/versions/3.10.13/envs/piel_0_57/lib/python3.10/site-packages/amaranth/hdl/xfrm.py:503" *)
+    if (rst) begin
+      \next_state$next  = 2'h0;
+    end
+  end
+  always @* begin
+    if (\$auto$verilog_backend.cc:2334:dump_module$1 ) begin end
+    (* full_case = 32'd1 *)
+    (* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:165" *)
+    casez (detector_in)
+      /* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:168" */
+      2'h0:
+          \phase_map_out$next  = 2'h0;
+      /* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:168" */
+      2'h1:
+          \phase_map_out$next  = 2'h2;
+      /* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:168" */
+      2'h2:
+          \phase_map_out$next  = 2'h3;
+      /* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:168" */
+      2'h3:
+          \phase_map_out$next  = 2'h3;
+    endcase
+    (* src = "/home/daquintero/.pyenv/versions/3.10.13/envs/piel_0_57/lib/python3.10/site-packages/amaranth/hdl/xfrm.py:503" *)
+    if (rst) begin
+      \phase_map_out$next  = 2'h0;
+    end
+  end
+endmodule
diff --git a/...2_digital_design_simulation/openlane_run/TruthTableModule/TruthTableModule/tb/__init__.py b/...2_digital_design_simulation/openlane_run/TruthTableModule/TruthTableModule/tb/__init__.py
diff --git a/...mples/02_digital_design_simulation/openlane_run/TruthTableModule/docs/README.md b/...mples/02_digital_design_simulation/openlane_run/TruthTableModule/docs/README.md
@@ -0,0 +1 @@
+TruthTableModule
diff --git a/docs/examples/02_digital_design_simulation/openlane_run/TruthTableModule/setup.py b/docs/examples/02_digital_design_simulation/openlane_run/TruthTableModule/setup.py
@@ -0,0 +1,11 @@
+#!/usr/bin/env python 
+from distutils.core import setup 
+
+setup(name="TruthTableModule", 
+	version="0.0.1", 
+	description="Example empty piel project."
+,	author="Dario Quintero", 
+	author_email="[email protected]", 
+	url="https://github.com/daquintero/piel", 
+	packages=['TruthTableModule'], 
+)
diff --git a/docs/examples/02_digital_design_simulation/our_truth_table_module.vcd b/docs/examples/02_digital_design_simulation/our_truth_table_module.vcd
diff --git a/docs/examples/02_digital_design_simulation/test.py b/docs/examples/02_digital_design_simulation/test.py
@@ -0,0 +1,32 @@
+from openlane.flows import SequentialFlow
+from openlane.steps import Yosys, Misc, OpenROAD, Magic, Netgen
+
+class MyFlow(SequentialFlow):
+    Steps = [
+        Yosys.Synthesis,
+        OpenROAD.Floorplan,
+        OpenROAD.TapEndcapInsertion,
+        OpenROAD.GeneratePDN,
+        OpenROAD.IOPlacement,
+        OpenROAD.GlobalPlacement,
+        OpenROAD.DetailedPlacement,
+        OpenROAD.GlobalRouting,
+        OpenROAD.DetailedRouting,
+        OpenROAD.FillInsertion,
+        Magic.StreamOut,
+        Magic.DRC,
+        Magic.SpiceExtraction,
+        Netgen.LVS
+    ]
+
+flow = MyFlow(
+    {
+        "PDK": "sky130A",
+        "DESIGN_NAME": "top",
+        "VERILOG_FILES": ["/home/daquintero/phd/piel/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/src/truth_table_module.v"],
+        "CLOCK_PORT": "clk",
+        "CLOCK_PERIOD": 10,
+    },
+    design_dir=".",
+)
+flow.start()
diff --git a/...esign_simulation/our_truth_table_module.v → ...al_design_simulation/truth_table_module.v b/...esign_simulation/our_truth_table_module.v → ...al_design_simulation/truth_table_module.v
@@ -1,30 +1,30 @@
-/* Generated by Amaranth Yosys 0.40 (PyPI ver 0.40.0.0.post95, git sha1 a1bb0255d) */
+/* Generated by Yosys 0.38 (git sha1 543faed9c8c, clang++ 17.0.6 -fPIC -Os) */
 
 (* top =  1  *)
 (* generator = "Amaranth" *)
 module top(phase_map_out, detector_in);
-  reg \$auto$verilog_backend.cc:2352:dump_module$1  = 0;
-  (* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:83" *)
+  reg \$auto$verilog_backend.cc:2334:dump_module$1  = 0;
+  (* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:84" *)
   input [1:0] detector_in;
   wire [1:0] detector_in;
-  (* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:87" *)
+  (* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:88" *)
   output [1:0] phase_map_out;
   reg [1:0] phase_map_out;
   always @* begin
-    if (\$auto$verilog_backend.cc:2352:dump_module$1 ) begin end
+    if (\$auto$verilog_backend.cc:2334:dump_module$1 ) begin end
     (* full_case = 32'd1 *)
-    (* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:113" *)
+    (* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:114" *)
     casez (detector_in)
-      /* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:116" */
+      /* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:117" */
       2'h0:
           phase_map_out = 2'h0;
-      /* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:116" */
+      /* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:117" */
       2'h1:
           phase_map_out = 2'h2;
-      /* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:116" */
+      /* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:117" */
       2'h2:
           phase_map_out = 2'h3;
-      /* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:116" */
+      /* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:117" */
       2'h3:
           phase_map_out = 2'h3;
     endcase