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daquintero · Jun 17, 2024 · 7391a6c · 7391a6c
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diff --git a/...img/examples/07_full_flow_demo_electronic_photonic/example_gtk_wave_signals.png b/...img/examples/07_full_flow_demo_electronic_photonic/example_gtk_wave_signals.png
diff --git a/docs/_static/resources/fsic_2024_presentation.odp b/docs/_static/resources/fsic_2024_presentation.odp
diff --git a/docs/examples/01_run_openlane_flow.py b/docs/examples/01_run_openlane_flow.py
diff --git a/docs/examples/02_digital_design_simulation/02_digital_design_simulation.py b/docs/examples/02_digital_design_simulation/02_digital_design_simulation.py
@@ -7,6 +7,7 @@
 # * `cocotb` is mainly used for writing testbenches in Python and verification of logic.
 
 import piel
+from piel.types import TruthTable
 
 import simple_design
 
@@ -20,18 +21,17 @@
 )
 
 # +
-# Uncomment this if you want to run it for the first time.
+# # Uncomment this if you want to run it for the first time.
 # piel.create_empty_piel_project(
 #     project_name="amaranth_driven_flow", parent_directory="../designs/"
 # )
 # -
 
 # We can also automate the `pip` installation of our local module:
 
-# +
+# ! pip install -e ../designs/amaranth_driven_flow
 #  Uncomment this if you want to run it for the first time.
 # piel.pip_install_local_module("../designs/amaranth_driven_flow")
-# -
 
 # We can check that this has been installed. You might need to restart your `jupyter` kernel.
 
@@ -64,7 +64,7 @@
     "detector_in": ["00", "01", "10", "11"],
     "phase_map_out": ["00", "10", "11", "11"],
 }
-detector_phase_truth_table = piel.types.TruthTable(
+detector_phase_truth_table = TruthTable(
     input_ports=["detector_in"],
     output_ports=["phase_map_out"],
     **detector_phase_truth_table_dictionary
@@ -158,7 +158,7 @@
     amaranth_module=our_truth_table_module,
     truth_table=detector_phase_truth_table,
     parent_directory=amaranth_driven_flow,
-    openlane_version="v1",
+    openlane_version="v2",
 )
 # -
 

diff --git a/docs/examples/02_digital_design_simulation/our_truth_table_module.v b/docs/examples/02_digital_design_simulation/our_truth_table_module.v
@@ -1,17 +1,17 @@
-/* Generated by Amaranth Yosys 0.40 (PyPI ver 0.40.0.0.post95, git sha1 a1bb0255d) */
+/* Generated by Yosys 0.38 (git sha1 543faed9c8c, clang++ 17.0.6 -fPIC -Os) */
 
 (* top =  1  *)
 (* generator = "Amaranth" *)
 module top(phase_map_out, detector_in);
-  reg \$auto$verilog_backend.cc:2352:dump_module$1  = 0;
+  reg \$auto$verilog_backend.cc:2334:dump_module$1  = 0;
   (* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:83" *)
   input [1:0] detector_in;
   wire [1:0] detector_in;
   (* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:87" *)
   output [1:0] phase_map_out;
   reg [1:0] phase_map_out;
   always @* begin
-    if (\$auto$verilog_backend.cc:2352:dump_module$1 ) begin end
+    if (\$auto$verilog_backend.cc:2334:dump_module$1 ) begin end
     (* full_case = 32'd1 *)
     (* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:113" *)
     casez (detector_in)

diff --git a/docs/examples/02_digital_design_simulation/our_truth_table_module.vcd b/docs/examples/02_digital_design_simulation/our_truth_table_module.vcd
@@ -1,5 +1,5 @@
 $comment Generated by Amaranth $end
-$date 2024-06-15 23:56:06.564080 $end
+$date 2024-06-17 13:50:14.247813 $end
 $timescale 1 ps $end
 $scope module bench $end
 $scope module top $end

diff --git a/docs/examples/04_spice_cosimulation/netlist.raw b/docs/examples/04_spice_cosimulation/netlist.raw
diff --git a/docs/examples/04_spice_cosimulation/netlist.sp b/docs/examples/04_spice_cosimulation/netlist.sp
@@ -1,41 +1,45 @@
 * `ngspice` Sim Input for `TransientTb`
 * Generated by `vlsirtools.NgspiceNetlister`
-*
+* 
 * Anonymous `circuit.Package`
 * Generated by `vlsirtools.NgspiceNetlister`
-*
+* 
 
 .SUBCKT Straight
-+ e1 e2
++ e1 e2 
 * No parameters
 
 rr1
-+ e1 e2
++ e1 e2 
 + 1000
 * No parameters
 
 
 .ENDS
 
 .SUBCKT TransientTb
-+ VSS
++ VSS 
 * No parameters
 
 vVPULSE
-+ VPULSE_p VSS
-+ pulse ('-1000m' '1000m' '1m' '10m' '10m' '75m' '100m')
++ VPULSE_p VSS 
++ pulse ('-1000m' '1000m' '1m' '10m' '10m' '75m' '100m') 
 * No parameters
 
 
 xdut
-+ VPULSE_p VSS
++ VPULSE_p VSS 
 + Straight
 * No parameters
 
 
 .ENDS
 
-xtop 0 TransientTb // Top-Level DUT
+xtop 0 TransientTb // Top-Level DUT 
 
 
 .tran 0.0001 0.2
+
+
+
+
diff --git a/...examples/04a_analogue_circuit_layout_simulation/04a_analogue_circuit_layout_simulation.py b/...examples/04a_analogue_circuit_layout_simulation/04a_analogue_circuit_layout_simulation.py
@@ -64,38 +64,38 @@
 
 # +
 # sky130.cells
+# sky130.cells["sky130_fd_pr__cap_vpp_02p4x04p6_m1m2_noshield"]()
 # -
 
-
 @h.module
 class SkyInv:
-    """An inverter, demonstrating using PDK modules"""
+    """ An inverter, demonstrating using PDK modules """
 
     # Create some IO
     i, o, VDD, VSS = h.Ports(4)
 
-    p = sky130_hdl21.Sky130MosParams(w=1, l=1)
+    p = sky130_hdl21.Sky130MosParams(w=1,l=1)
 
     # And create some transistors!
     ps = sky130_hdl21.primitives.PMOS_1p8V_STD(p)(d=o, g=i, s=VDD, b=VDD)
     ns = sky130_hdl21.primitives.NMOS_1p8V_STD(p)(d=VSS, g=i, s=o, b=VSS)
 
 
-# ## Schematic-Driven-Layout
-
+# ### Schematic-Driven-Layout
+#
 # A common analogue design flow is called schematic-driven-layout. What this entails, fundamentally, is that we design a circuit through a schematic, and then use that schematic to instruct, extract, constrain, and/or verify our circuit chip layout. This flow uses layout elements that are connected or tied to schematic symbols, and unique names that allow for identification and connectivity relationship.
 #
 # -  You can read [how this is done in Cadence](https://web.njit.edu/~tyson/cadence%20Layout_Tutorial.pdf)
 #
 # In an open-source flow, this could be, for example, demonstrated by creating a circuit using the `hdl21 schematic` tools. Each symbol would reference a specific `PCell` in the PDK. Now, we would use this individual element cell name to connect and extract to the `SPICE` model and also to the `layout` GDS cell. This allows us to connect to the separate tools for simulation and layout.
 #
 # Say, we can then extract a netlist from the schematic with individual cell names and PDK cells identifiers. We could in `gdsfactory` map these PDK cell identifiers to instantiate the elements in a layout. We can then use this instantated cells to perform some automatic or
-
-# ### Manually editing the `SPICE`-generated `gdsfactory` component YAML
 #
 # It is important to know that with the SPICE-generated YAML, we cannot actually create a layout on its own. This is because the SPICE models do not exactly directly map to layout instances. SPICE models can represent performance corners for the same device, with multiple temperature or yield quality variations. As such, we need to assign the corresponding gds we want to layout for our specific schematic model.
 
-example_inverter_manual_yaml = piel.generate_raw_yaml_from_module(SkyInv)
+example_inverter_manual_yaml = piel.generate_raw_yaml_from_module(
+    SkyInv
+)
 print(example_inverter_manual_yaml)
 
 example_inverter_manual_yaml = """
@@ -158,10 +158,10 @@ class SkyInv:
   i: ps,g
   o: ps,d
 """
-with open("example_inverter_manual.schem.yaml", "w") as file:
-    file.write(example_inverter_manual_yaml)
+with open("example_inverter_manual.schem.yaml", 'w') as file:
+        file.write(example_inverter_manual_yaml)
 
-# ### Automatically mapping layout instances to the YAML
+# ### Automatically mapping layout instances to the YAML - Inverter
 
 example_inverter_schematic_editor = piel.hdl21_module_to_schematic_editor(
     module=SkyInv,
@@ -170,41 +170,17 @@ class SkyInv:
 example_inverter_schematic_editor.visualize()
 
 example_inverter_layout = "example_inverter_auto.layout.yaml"
-example_inverter_schematic_editor.instantiate_layout(
-    example_inverter_layout,
-    default_router="get_bundle",
-    default_cross_section="xs_metal1",
-)
+example_inverter_schematic_editor.instantiate_layout(example_inverter_layout, default_router="get_bundle", default_cross_section="xs_metal1")
 c = gf.read.from_yaml(example_inverter_layout)
 c.plot()
 
-# ### More Advanced Example
-
-import sky130_hdl21
-
-# +
-# help(sky130_hdl21)
-# help(sky130_hdl21.primitives)
-# sky130_hdl21.primitives.PMOS_1p8V_STD
-# sky130_hdl21.ress
-# -
-
-# We have now extracted our spice elements and our connectivity. Let's explore what we have there:
-
-# + active=""
-# # Current TODOs
+# ### More Advanced Example - R2R DAC
 #
-# 1. Update the extraction function to add xschem compatibility.
-# 2. Create the mapping between the extracted netlist and the corresponding SKY130nm elements.
+#
+# An example of using `hdl21.ExternalModule`s representing an implementation technology/ PDK
+# in a parametric resistive DAC generator mapping to a gdsfactory implementation.
 
 # +
-"""
-# Resistor DAC Example
-
-An example of using `ExternalModule`s representing an implementation technology/ PDK
-in a parametric resistive DAC generator.
-"""
-
 import sys
 from typing import Optional
 
@@ -411,8 +387,20 @@ class MuxTree:
 )
 
 # Netlist in a handful of formats
-duts = [rladder(rparams), mux_tree(mparams)]
+duts = [rladder(rparams), ]
 # h.netlist(duts, sys.stdout, fmt="verilog")
 # h.netlist(duts, sys.stdout, fmt="spectre")
-h.netlist(duts, sys.stdout, fmt="spice")
+# h.netlist(duts, sys.stdout, fmt="spice")
 # h.netlist(duts, sys.stdout, fmt="xyce")
+# -
+
+example_resistor_ladder_schematic_editor = piel.hdl21_module_to_schematic_editor(
+    module=rladder(rparams),
+    yaml_schematic_file_name="rladder.schem.yaml",
+)
+example_resistor_ladder_schematic_editor.visualize()
+
+example_inverter_layout = "example_inverter_auto.layout.yaml"
+example_inverter_schematic_editor.instantiate_layout(example_inverter_layout, default_router="get_bundle", default_cross_section="xs_metal1")
+c = gf.read.from_yaml(example_inverter_layout)
+c.plot()