FEAT: Further openlane integrations and openlane2 examples (#45)

* BUG: Begun further tools integrations

* FEAT: Working runs format filtering

* FEAT: Working openlane 2 automation

* FEAT: Add openlane2 screenshots

* FEAT: Include openlane 2 generated files in examples

* FEAT: Working truth table deployment

docs/autoapi/piel/index.rst

@@ -89,7 +89,7 @@ Functions
    piel.get_input_ports_index
    piel.get_matched_ports_tuple_index
    piel.get_design_from_openlane_migration
-   piel.find_design_run
+   piel.find_latest_design_run
    piel.check_config_json_exists_openlane_v1
    piel.check_design_exists_openlane_v1
    piel.configure_and_run_design_openlane_v1
@@ -959,7 +959,7 @@ Attributes
    :returns: None
 
 
-.. py:function:: find_design_run(design_directory: piel.config.piel_path_types, run_name: str | None = None) -> pathlib.Path
+.. py:function:: find_latest_design_run(design_directory: piel.config.piel_path_types, run_name: str | None = None) -> pathlib.Path
 
    For a given `design_directory`, the `openlane` output can be found in the `runs` subdirectory.
 

docs/autoapi/piel/tools/index.rst

@@ -38,7 +38,7 @@ Functions
    piel.tools.get_input_ports_index
    piel.tools.get_matched_ports_tuple_index
    piel.tools.get_design_from_openlane_migration
-   piel.tools.find_design_run
+   piel.tools.find_latest_design_run
    piel.tools.check_config_json_exists_openlane_v1
    piel.tools.check_design_exists_openlane_v1
    piel.tools.configure_and_run_design_openlane_v1
@@ -300,7 +300,7 @@ Attributes
    :returns: None
 
 
-.. py:function:: find_design_run(design_directory: piel.config.piel_path_types, run_name: str | None = None) -> pathlib.Path
+.. py:function:: find_latest_design_run(design_directory: piel.config.piel_path_types, run_name: str | None = None) -> pathlib.Path
 
    For a given `design_directory`, the `openlane` output can be found in the `runs` subdirectory.
 

docs/autoapi/piel/tools/openlane/defaults/index.rst

@@ -11,7 +11,7 @@ Module Contents
 
 
 
-.. py:data:: test_basic_open_lane_configuration
+.. py:data:: test_basic_open_lane_configuration_v1
 
 
 

docs/autoapi/piel/tools/openlane/index.rst

@@ -36,7 +36,7 @@ Functions
 .. autoapisummary::
 
    piel.tools.openlane.get_design_from_openlane_migration
-   piel.tools.openlane.find_design_run
+   piel.tools.openlane.find_latest_design_run
    piel.tools.openlane.check_config_json_exists_openlane_v1
    piel.tools.openlane.check_design_exists_openlane_v1
    piel.tools.openlane.configure_and_run_design_openlane_v1
@@ -88,7 +88,7 @@ Functions
    :returns: None
 
 
-.. py:function:: find_design_run(design_directory: piel.config.piel_path_types, run_name: str | None = None) -> pathlib.Path
+.. py:function:: find_latest_design_run(design_directory: piel.config.piel_path_types, run_name: str | None = None) -> pathlib.Path
 
    For a given `design_directory`, the `openlane` output can be found in the `runs` subdirectory.
 

docs/autoapi/piel/tools/openlane/utils/index.rst

@@ -13,11 +13,11 @@ Functions
 
 .. autoapisummary::
 
-   piel.tools.openlane.utils.find_design_run
+   piel.tools.openlane.utils.find_latest_design_run
 
 
 
-.. py:function:: find_design_run(design_directory: piel.config.piel_path_types, run_name: str | None = None) -> pathlib.Path
+.. py:function:: find_latest_design_run(design_directory: piel.config.piel_path_types, run_name: str | None = None) -> pathlib.Path
 
    For a given `design_directory`, the `openlane` output can be found in the `runs` subdirectory.
 

docs/examples/01_run_openlane_flow.py

@@ -132,7 +132,7 @@
 
 # We can find which is the latest design run
 
-latest_design_run_directory = piel.find_design_run(
+latest_design_run_directory = piel.find_latest_design_run(
     design_directory="./designs" / piel.return_path("inverter"),
 )
 latest_design_run_directory
@@ -152,7 +152,7 @@
 
 # First, we get the directory of the latest run:
 
-latest_run_output = piel.find_design_run(
+latest_run_output = piel.find_latest_design_run(
     design_directory="./designs" / piel.return_path("inverter"),
 )
 latest_run_output
@@ -284,6 +284,58 @@
 
 # ## OpenLane V2 Flow
 
-piel.run_openlane_flow(
-    design_directory="/foss/designs/spm",
+# It might be desired to easily go from a design directory to an actual silicon chip purely from python. In this section of the example we will use the digital design files in an `amaranth`-generated design flow and use `openlane2` to perform the hardening of the logic.
+#
+# There is further documentation on migrating from the `Openlane v1` flow to `v2` in the following links:
+
+# You need to make sure you have installed `amaranth_driven_flow` as part of the `02_digital_design_simulation` example instructions.
+
+import amaranth_driven_flow
+import piel
+
+# The project directory is found here if you have installed the project
+
+piel.return_path(amaranth_driven_flow)
+
+openlane_2_run_amaranth_flow = piel.run_openlane_flow(
+    design_directory=amaranth_driven_flow,
+    only_generate_flow_setup=True,
+)
+
+# This should generate a `openlane 2` driven layout in the `amaranth_driven_flow` directory if you change the `only_generate_configuration` flag to `True`. Let's list the available runs in this project:
+
+all_amaranth_driven_design_runs = piel.find_all_design_runs(
+    design_directory=amaranth_driven_flow,
+)
+all_amaranth_driven_design_runs
+
+# ```python
+# {'v2': [PosixPath('/home/daquintero/piel/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/runs/RUN_2023-09-06_14-17-18')],
+#  'v1': [PosixPath('/home/daquintero/piel/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/runs/RUN_2023.08.22_00.06.09')]}
+# ```
+
+latest_amaranth_driven_openlane_runs = piel.find_latest_design_run(
+    design_directory=amaranth_driven_flow,
+)
+latest_amaranth_driven_openlane_runs
+
+# We can check what is the path to our generated `gds` file accordingly:
+
+piel.get_gds_path_from_design_run(
+    design_directory=amaranth_driven_flow,
 )
+
+# It is quite easy to visualise it on the jupyter lab using the `gdsfactory` integration widget:
+
+amaranth_driven_flow_component = piel.create_gdsfactory_component_from_openlane(
+    design_directory=amaranth_driven_flow,
+)
+amaranth_driven_flow_component
+
+# ![amaranth_driven_flow_klive](../_static/img/examples/01b_gdsfactory_layout_integation/amaranth_driven_flow_klive.PNG)
+
+# Very cool! So now we can interact and generate `openlane 2` designs easily. Let's explore now getting some design metrics out of this design.
+
+# ### Deployment and Timing of Large-Scale `openlane2` designs
+#
+# One common and powerful aspect of this tool is the large-scale deployment of `openlane 2`

docs/examples/02_digital_design_simulation/02_digital_design_simulation.py

@@ -7,6 +7,7 @@
 # * `cocotb` is mainly used for writing testbenches in Python and verification of logic.
 
 import piel
+
 import simple_design
 
 # In this example, we will use `amaranth` to perform some design and then simulations, so let's create a suitable project structure based on our initial `simple_design`, where we will output our files.
@@ -135,7 +136,7 @@
 
 # ### Integration with the `openlane v2` flow
 
-# You may want, for example, to layout this design as an `openlane` design. There are different flows of how to achieve this. We know, for example, that we have a design directory where we want to save the outputs of the `openlane` runs. It will impelement the design using the `openlane v2` versions:
+# You may want, for example, to layout this design as an `openlane` design. There are different flows of how to achieve this. We know, for example, that we have a design directory where we want to save the outputs of the `openlane` runs. It will implement the design using the `openlane v2` versions:
 
 # +
 from piel.integration.amaranth_openlane import (

docs/examples/02_digital_design_simulation/our_truth_table_module.v

@@ -1,31 +1,31 @@
-/* Generated by Amaranth Yosys 0.25 (PyPI ver 0.25.0.0.post74, git sha1 e02b7f64b) */
+/* Generated by Yosys 0.30+48 (git sha1 14d50a176d5, clang++ 11.1.0 -fPIC -Os) */
 
 (* \amaranth.hierarchy  = "top" *)
 (* top =  1  *)
 (* generator = "Amaranth" *)
 module top(phase_map_out, detector_in);
-  reg \$auto$verilog_backend.cc:2083:dump_module$1  = 0;
-  (* src = "c:\\users\\dario\\documents\\phd\\piel\\piel\\tools\\amaranth\\construct.py:42" *)
+  reg \$auto$verilog_backend.cc:2097:dump_module$1  = 0;
+  (* src = "/home/daquintero/piel/piel/tools/amaranth/construct.py:43" *)
   input [1:0] detector_in;
   wire [1:0] detector_in;
-  (* src = "c:\\users\\dario\\documents\\phd\\piel\\piel\\tools\\amaranth\\construct.py:42" *)
+  (* src = "/home/daquintero/piel/piel/tools/amaranth/construct.py:43" *)
   output [1:0] phase_map_out;
   reg [1:0] phase_map_out;
   always @* begin
-    if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
+    if (\$auto$verilog_backend.cc:2097:dump_module$1 ) begin end
     (* full_case = 32'd1 *)
-    (* src = "c:\\users\\dario\\documents\\phd\\piel\\piel\\tools\\amaranth\\construct.py:56" *)
+    (* src = "/home/daquintero/piel/piel/tools/amaranth/construct.py:57" *)
     casez (detector_in)
-      /* src = "c:\\users\\dario\\documents\\phd\\piel\\piel\\tools\\amaranth\\construct.py:59" */
+      /* src = "/home/daquintero/piel/piel/tools/amaranth/construct.py:60" */
       2'h0:
           phase_map_out = 2'h0;
-      /* src = "c:\\users\\dario\\documents\\phd\\piel\\piel\\tools\\amaranth\\construct.py:59" */
+      /* src = "/home/daquintero/piel/piel/tools/amaranth/construct.py:60" */
       2'h1:
           phase_map_out = 2'h2;
-      /* src = "c:\\users\\dario\\documents\\phd\\piel\\piel\\tools\\amaranth\\construct.py:59" */
+      /* src = "/home/daquintero/piel/piel/tools/amaranth/construct.py:60" */
       2'h2:
           phase_map_out = 2'h3;
-      /* src = "c:\\users\\dario\\documents\\phd\\piel\\piel\\tools\\amaranth\\construct.py:59" */
+      /* src = "/home/daquintero/piel/piel/tools/amaranth/construct.py:60" */
       2'h3:
           phase_map_out = 2'h3;
     endcase

docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/config.json

@@ -1,4 +1,5 @@
 {
+    "PDK": "sky130A",
     "DESIGN_NAME": "top",
     "VERILOG_FILES": "dir::src/*.v",
     "RUN_CTS": false,

docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/runs/RUN_2023-09-06_14-17-18/02-checker-linttimingconstructs/config.json

@@ -0,0 +1,176 @@
+{
+    "STD_CELL_LIBRARY": "sky130_fd_sc_hd",
+    "VDD_PIN": "VPWR",
+    "VDD_PIN_VOLTAGE": 1.8,
+    "GND_PIN": "VGND",
+    "WIRE_LENGTH_THRESHOLD": null,
+    "TECH_LEFS": {
+        "nom_*": "/home/daquintero/.volare/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef",
+        "min_*": "/home/daquintero/.volare/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__min.tlef",
+        "max_*": "/home/daquintero/.volare/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__max.tlef"
+    },
+    "GPIO_PADS_LEF": [
+        "/home/daquintero/.volare/sky130A/libs.ref/sky130_fd_io/lef/sky130_fd_io.lef",
+        "/home/daquintero/.volare/sky130A/libs.ref/sky130_fd_io/lef/sky130_ef_io.lef"
+    ],
+    "GPIO_PADS_LEF_CORE_SIDE": [
+        "/home/daquintero/.volare/sky130A/libs.tech/openlane/custom_cells/lef/sky130_fd_io_core.lef",
+        "/home/daquintero/.volare/sky130A/libs.tech/openlane/custom_cells/lef/sky130_ef_io_core.lef"
+    ],
+    "GPIO_PADS_VERILOG": [
+        "/home/daquintero/.volare/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"
+    ],
+    "GPIO_PADS_PREFIX": [
+        "sky130_fd_io",
+        "sky130_ef_io"
+    ],
+    "PRIMARY_SIGNOFF_TOOL": "magic",
+    "DEFAULT_MAX_TRAN": null,
+    "DATA_WIRE_RC_LAYER": "met2",
+    "CLOCK_WIRE_RC_LAYER": "met5",
+    "DEFAULT_CORNER": "nom_tt_025C_1v80",
+    "STA_CORNERS": [
+        "nom_tt_025C_1v80",
+        "nom_ss_100C_1v60",
+        "nom_ff_n40C_1v95",
+        "min_tt_025C_1v80",
+        "min_ss_100C_1v60",
+        "min_ff_n40C_1v95",
+        "max_tt_025C_1v80",
+        "max_ss_100C_1v60",
+        "max_ff_n40C_1v95"
+    ],
+    "FP_TRACKS_INFO": "/home/daquintero/.volare/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tracks.info",
+    "FP_TAPCELL_DIST": 13,
+    "FP_IO_HLAYER": "met3",
+    "FP_IO_VLAYER": "met2",
+    "RT_MIN_LAYER": "met1",
+    "RT_MAX_LAYER": "met5",
+    "SCL_GROUND_PINS": [
+        "VGND",
+        "VNB"
+    ],
+    "SCL_POWER_PINS": [
+        "VPWR",
+        "VPB"
+    ],
+    "FILL_CELL": [
+        "sky130_fd_sc_hd__fill*"
+    ],
+    "DECAP_CELL": [
+        "sky130_ef_sc_hd__decap_12",
+        "sky130_fd_sc_hd__decap_8",
+        "sky130_fd_sc_hd__decap_6",
+        "sky130_fd_sc_hd__decap_4",
+        "sky130_fd_sc_hd__decap_3"
+    ],
+    "LIB": {
+        "*_tt_025C_1v80": [
+            "/home/daquintero/.volare/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib"
+        ],
+        "*_ss_100C_1v60": [
+            "/home/daquintero/.volare/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
+        ],
+        "*_ff_n40C_1v95": [
+            "/home/daquintero/.volare/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
+        ]
+    },
+    "CELL_LEFS": [
+        "/home/daquintero/.volare/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef",
+        "/home/daquintero/.volare/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd.lef"
+    ],
+    "CELL_GDS": [
+        "/home/daquintero/.volare/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds"
+    ],
+    "CELL_VERILOG_MODELS": [
+        "/home/daquintero/.volare/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v",
+        "/home/daquintero/.volare/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
+    ],
+    "CELL_BB_VERILOG_MODELS": [
+        "/home/daquintero/.volare/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd__blackbox_pp.v",
+        "/home/daquintero/.volare/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd__blackbox.v"
+    ],
+    "CELL_SPICE_MODELS": [
+        "/home/daquintero/.volare/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_8.spice",
+        "/home/daquintero/.volare/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fakediode_2.spice",
+        "/home/daquintero/.volare/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice",
+        "/home/daquintero/.volare/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_12.spice",
+        "/home/daquintero/.volare/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_4.spice",
+        "/home/daquintero/.volare/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_12.spice"
+    ],
+    "SYNTH_EXCLUSION_CELL_LIST": "/home/daquintero/.volare/sky130A/libs.tech/openlane/sky130_fd_sc_hd/no_synth.cells",
+    "PNR_EXCLUSION_CELL_LIST": "/home/daquintero/.volare/sky130A/libs.tech/openlane/sky130_fd_sc_hd/drc_exclude.cells",
+    "OUTPUT_CAP_LOAD": 33.442,
+    "MAX_FANOUT_CONSTRAINT": 10,
+    "MAX_TRANSITION_CONSTRAINT": 0.75,
+    "CLOCK_UNCERTAINTY_CONSTRAINT": 0.25,
+    "CLOCK_TRANSITION_CONSTRAINT": 0.15,
+    "TIME_DERATING_CONSTRAINT": 5,
+    "IO_DELAY_CONSTRAINT": 20,
+    "SYNTH_DRIVING_CELL": "sky130_fd_sc_hd__inv_2/Y",
+    "SYNTH_CLK_DRIVING_CELL": null,
+    "SYNTH_TIEHI_CELL": "sky130_fd_sc_hd__conb_1/HI",
+    "SYNTH_TIELO_CELL": "sky130_fd_sc_hd__conb_1/LO",
+    "SYNTH_BUFFER_CELL": "sky130_fd_sc_hd__buf_2/A/X",
+    "CTS_ROOT_BUFFER": "sky130_fd_sc_hd__clkbuf_16",
+    "CTS_CLK_BUFFERS": [
+        "sky130_fd_sc_hd__clkbuf_8",
+        "sky130_fd_sc_hd__clkbuf_4",
+        "sky130_fd_sc_hd__clkbuf_2"
+    ],
+    "CTS_MAX_CAP": 1.53169,
+    "FP_WELLTAP_CELL": "sky130_fd_sc_hd__tapvpwrvgnd_1",
+    "FP_ENDCAP_CELL": "sky130_fd_sc_hd__decap_3",
+    "IGNORE_DISCONNECTED_MODULES": [
+        "sky130_fd_sc_hd__conb_1"
+    ],
+    "PLACE_SITE": "unithd",
+    "PLACE_SITE_WIDTH": 0.46,
+    "PLACE_SITE_HEIGHT": 2.72,
+    "GPL_CELL_PADDING": 0,
+    "DPL_CELL_PADDING": 0,
+    "CELL_PAD_EXCLUDE": [
+        "sky130_fd_sc_hd__tap*",
+        "sky130_fd_sc_hd__decap*",
+        "sky130_ef_sc_hd__decap*",
+        "sky130_fd_sc_hd__fill*"
+    ],
+    "DIODE_CELL": "sky130_fd_sc_hd__diode_2/DIODE",
+    "GRT_LAYER_ADJUSTMENTS": [
+        0.99,
+        0,
+        0,
+        0,
+        0,
+        0
+    ],
+    "DESIGN_DIR": "/home/daquintero/piel/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow",
+    "PDK_ROOT": "/home/daquintero/.volare",
+    "DESIGN_NAME": "top",
+    "PDK": "sky130A",
+    "CLOCK_PERIOD": 10,
+    "CLOCK_PORT": null,
+    "CLOCK_NET": null,
+    "VDD_NETS": null,
+    "GND_NETS": null,
+    "DIE_AREA": "0 0 34.5 57.12",
+    "MACROS": null,
+    "EXTRA_LEFS": null,
+    "EXTRA_VERILOG_MODELS": null,
+    "EXTRA_SPICE_MODELS": null,
+    "EXTRA_LIBS": null,
+    "EXTRA_GDS_FILES": null,
+    "FP_CONTEXT_DEF": null,
+    "FP_CONTEXT_LEF": null,
+    "FP_PADFRAME_CFG": null,
+    "GRT_OBS": null,
+    "LVS_INSERT_POWER_PINS": true,
+    "RUN_CVC": true,
+    "LEC_ENABLE": false,
+    "CHECK_ASSIGN_STATEMENTS": false,
+    "QUIT_ON_LINTER_TIMING_CONSTRUCTS": true,
+    "meta": {
+        "openlane_version": "2.0.0b12",
+        "step": "Checker.LintTimingConstructs"
+    }
+}