finally understood it's a path situation with openlane

daquintero · Jun 18, 2024 · 9855920 · 9855920
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diff --git a/...s/02_digital_design_simulation/openlane_run/TruthTableModule/TruthTableModule/__init__.py b/...s/02_digital_design_simulation/openlane_run/TruthTableModule/TruthTableModule/__init__.py
diff --git a/...tal_design_simulation/openlane_run/TruthTableModule/TruthTableModule/analogue/__init__.py b/...tal_design_simulation/openlane_run/TruthTableModule/TruthTableModule/analogue/__init__.py
diff --git a/...l_design_simulation/openlane_run/TruthTableModule/TruthTableModule/components/__init__.py b/...l_design_simulation/openlane_run/TruthTableModule/TruthTableModule/components/__init__.py
diff --git a/...simulation/openlane_run/TruthTableModule/TruthTableModule/components/analogue/__init__.py b/...simulation/openlane_run/TruthTableModule/TruthTableModule/components/analogue/__init__.py
diff --git a/..._simulation/openlane_run/TruthTableModule/TruthTableModule/components/digital/__init__.py b/..._simulation/openlane_run/TruthTableModule/TruthTableModule/components/digital/__init__.py
diff --git a/...imulation/openlane_run/TruthTableModule/TruthTableModule/components/photonics/__init__.py b/...imulation/openlane_run/TruthTableModule/TruthTableModule/components/photonics/__init__.py
diff --git a/...gital_design_simulation/openlane_run/TruthTableModule/TruthTableModule/models/__init__.py b/...gital_design_simulation/openlane_run/TruthTableModule/TruthTableModule/models/__init__.py
diff --git a/...ign_simulation/openlane_run/TruthTableModule/TruthTableModule/models/analogue/__init__.py b/...ign_simulation/openlane_run/TruthTableModule/TruthTableModule/models/analogue/__init__.py
diff --git a/...gn_simulation/openlane_run/TruthTableModule/TruthTableModule/models/frequency/__init__.py b/...gn_simulation/openlane_run/TruthTableModule/TruthTableModule/models/frequency/__init__.py
diff --git a/...design_simulation/openlane_run/TruthTableModule/TruthTableModule/models/logic/__init__.py b/...design_simulation/openlane_run/TruthTableModule/TruthTableModule/models/logic/__init__.py
diff --git a/...ign_simulation/openlane_run/TruthTableModule/TruthTableModule/models/physical/__init__.py b/...ign_simulation/openlane_run/TruthTableModule/TruthTableModule/models/physical/__init__.py
diff --git a/...gn_simulation/openlane_run/TruthTableModule/TruthTableModule/models/transient/__init__.py b/...gn_simulation/openlane_run/TruthTableModule/TruthTableModule/models/transient/__init__.py
diff --git a/...tal_design_simulation/openlane_run/TruthTableModule/TruthTableModule/photonic/__init__.py b/...tal_design_simulation/openlane_run/TruthTableModule/TruthTableModule/photonic/__init__.py
diff --git a/...design_simulation/openlane_run/TruthTableModule/TruthTableModule/src/truth_table_module.v b/...design_simulation/openlane_run/TruthTableModule/TruthTableModule/src/truth_table_module.v
@@ -0,0 +1,89 @@
+/* Generated by Yosys 0.38 (git sha1 543faed9c8c, clang++ 17.0.6 -fPIC -Os) */
+
+(* top =  1  *)
+(* generator = "Amaranth" *)
+module top(phase_map_out, clk, rst, detector_in);
+  reg \$auto$verilog_backend.cc:2334:dump_module$1  = 0;
+  (* src = "/home/daquintero/.pyenv/versions/3.10.13/envs/piel_0_57/lib/python3.10/site-packages/amaranth/hdl/ir.py:508" *)
+  input clk;
+  wire clk;
+  (* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:139" *)
+  input [1:0] detector_in;
+  wire [1:0] detector_in;
+  (* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:160" *)
+  reg [1:0] next_state = 2'h0;
+  (* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:160" *)
+  reg [1:0] \next_state$next ;
+  (* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:141" *)
+  output [1:0] phase_map_out;
+  reg [1:0] phase_map_out = 2'h0;
+  (* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:141" *)
+  reg [1:0] \phase_map_out$next ;
+  (* src = "/home/daquintero/.pyenv/versions/3.10.13/envs/piel_0_57/lib/python3.10/site-packages/amaranth/hdl/ir.py:508" *)
+  input rst;
+  wire rst;
+  (* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:154" *)
+  reg [1:0] state = 2'h0;
+  (* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:154" *)
+  reg [1:0] \state$next ;
+  always @(posedge clk)
+    state <= \state$next ;
+  always @(posedge clk)
+    next_state <= \next_state$next ;
+  always @(posedge clk)
+    phase_map_out <= \phase_map_out$next ;
+  always @* begin
+    if (\$auto$verilog_backend.cc:2334:dump_module$1 ) begin end
+    \state$next  = next_state;
+    (* src = "/home/daquintero/.pyenv/versions/3.10.13/envs/piel_0_57/lib/python3.10/site-packages/amaranth/hdl/xfrm.py:503" *)
+    if (rst) begin
+      \state$next  = 2'h0;
+    end
+  end
+  always @* begin
+    if (\$auto$verilog_backend.cc:2334:dump_module$1 ) begin end
+    (* full_case = 32'd1 *)
+    (* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:165" *)
+    casez (detector_in)
+      /* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:168" */
+      2'h0:
+          \next_state$next  = 2'h0;
+      /* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:168" */
+      2'h1:
+          \next_state$next  = 2'h1;
+      /* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:168" */
+      2'h2:
+          \next_state$next  = 2'h2;
+      /* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:168" */
+      2'h3:
+          \next_state$next  = 2'h3;
+    endcase
+    (* src = "/home/daquintero/.pyenv/versions/3.10.13/envs/piel_0_57/lib/python3.10/site-packages/amaranth/hdl/xfrm.py:503" *)
+    if (rst) begin
+      \next_state$next  = 2'h0;
+    end
+  end
+  always @* begin
+    if (\$auto$verilog_backend.cc:2334:dump_module$1 ) begin end
+    (* full_case = 32'd1 *)
+    (* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:165" *)
+    casez (detector_in)
+      /* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:168" */
+      2'h0:
+          \phase_map_out$next  = 2'h0;
+      /* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:168" */
+      2'h1:
+          \phase_map_out$next  = 2'h2;
+      /* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:168" */
+      2'h2:
+          \phase_map_out$next  = 2'h3;
+      /* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:168" */
+      2'h3:
+          \phase_map_out$next  = 2'h3;
+    endcase
+    (* src = "/home/daquintero/.pyenv/versions/3.10.13/envs/piel_0_57/lib/python3.10/site-packages/amaranth/hdl/xfrm.py:503" *)
+    if (rst) begin
+      \phase_map_out$next  = 2'h0;
+    end
+  end
+endmodule
diff --git a/...2_digital_design_simulation/openlane_run/TruthTableModule/TruthTableModule/tb/__init__.py b/...2_digital_design_simulation/openlane_run/TruthTableModule/TruthTableModule/tb/__init__.py
diff --git a/...mples/02_digital_design_simulation/openlane_run/TruthTableModule/docs/README.md b/...mples/02_digital_design_simulation/openlane_run/TruthTableModule/docs/README.md
@@ -0,0 +1 @@
+TruthTableModule
diff --git a/docs/examples/02_digital_design_simulation/openlane_run/TruthTableModule/setup.py b/docs/examples/02_digital_design_simulation/openlane_run/TruthTableModule/setup.py
@@ -0,0 +1,11 @@
+#!/usr/bin/env python 
+from distutils.core import setup 
+
+setup(name="TruthTableModule", 
+	version="0.0.1", 
+	description="Example empty piel project."
+,	author="Dario Quintero", 
+	author_email="[email protected]", 
+	url="https://github.com/daquintero/piel", 
+	packages=['TruthTableModule'], 
+)
diff --git a/docs/examples/02_digital_design_simulation/test.py b/docs/examples/02_digital_design_simulation/test.py
@@ -0,0 +1,32 @@
+from openlane.flows import SequentialFlow
+from openlane.steps import Yosys, Misc, OpenROAD, Magic, Netgen
+
+class MyFlow(SequentialFlow):
+    Steps = [
+        Yosys.Synthesis,
+        OpenROAD.Floorplan,
+        OpenROAD.TapEndcapInsertion,
+        OpenROAD.GeneratePDN,
+        OpenROAD.IOPlacement,
+        OpenROAD.GlobalPlacement,
+        OpenROAD.DetailedPlacement,
+        OpenROAD.GlobalRouting,
+        OpenROAD.DetailedRouting,
+        OpenROAD.FillInsertion,
+        Magic.StreamOut,
+        Magic.DRC,
+        Magic.SpiceExtraction,
+        Netgen.LVS
+    ]
+
+flow = MyFlow(
+    {
+        "PDK": "sky130A",
+        "DESIGN_NAME": "top",
+        "VERILOG_FILES": ["/home/daquintero/phd/piel/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/src/truth_table_module.v"],
+        "CLOCK_PORT": "clk",
+        "CLOCK_PERIOD": 10,
+    },
+    design_dir=".",
+)
+flow.start()
diff --git a/docs/examples/02_digital_design_simulation/truth_table_module.v b/docs/examples/02_digital_design_simulation/truth_table_module.v
@@ -0,0 +1,32 @@
+/* Generated by Yosys 0.38 (git sha1 543faed9c8c, clang++ 17.0.6 -fPIC -Os) */
+
+(* top =  1  *)
+(* generator = "Amaranth" *)
+module top(phase_map_out, detector_in);
+  reg \$auto$verilog_backend.cc:2334:dump_module$1  = 0;
+  (* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:84" *)
+  input [1:0] detector_in;
+  wire [1:0] detector_in;
+  (* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:88" *)
+  output [1:0] phase_map_out;
+  reg [1:0] phase_map_out;
+  always @* begin
+    if (\$auto$verilog_backend.cc:2334:dump_module$1 ) begin end
+    (* full_case = 32'd1 *)
+    (* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:114" *)
+    casez (detector_in)
+      /* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:117" */
+      2'h0:
+          phase_map_out = 2'h0;
+      /* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:117" */
+      2'h1:
+          phase_map_out = 2'h2;
+      /* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:117" */
+      2'h2:
+          phase_map_out = 2'h3;
+      /* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:117" */
+      2'h3:
+          phase_map_out = 2'h3;
+    endcase
+  end
+endmodule
diff --git a/docs/examples/04a_analogue_circuit_layout_simulation/rladder.layout.yaml b/docs/examples/04a_analogue_circuit_layout_simulation/rladder.layout.yaml
@@ -0,0 +1,30 @@
+schema_version: 1
+schema: null
+instances:
+  ps:
+    component: sky130_fd_pr__rf_pfet_01v8_mcM04W3p00L0p15
+    settings: {}
+  ns:
+    component: sky130_fd_pr__rf_nfet_01v8_aM02W1p65L0p15
+    settings: {}
+placements:
+  ps: {x: null, y: null, port: null, rotation: 0, dx: null, dy: null, mirror: null}
+  ns: {x: null, y: null, port: null, rotation: 0, dx: null, dy: null, mirror: null}
+routes:
+  r0:
+    routing_strategy: get_bundle
+    settings: {cross_section: xs_metal1, separation: 5.0}
+    links: {'ps,DRAIN': 'ns,SOURCE'}
+  r1:
+    routing_strategy: get_bundle
+    settings: {cross_section: xs_metal1, separation: 5.0}
+    links: {'ps,GATE': 'ns,GATE'}
+  r2:
+    routing_strategy: get_bundle
+    settings: {cross_section: xs_metal1, separation: 5.0}
+    links: {'ns,GATE': 'ps,GATE'}
+  r3:
+    routing_strategy: get_bundle
+    settings: {cross_section: xs_metal1, separation: 5.0}
+    links: {'ns,SOURCE': 'ps,DRAIN'}
+ports: {}
diff --git a/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/__init__.py b/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/__init__.py
diff --git a/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/analogue/__init__.py b/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/analogue/__init__.py
diff --git a/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/components/__init__.py b/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/components/__init__.py
diff --git a/...xamples/designs/amaranth_driven_flow/amaranth_driven_flow/components/analogue/__init__.py b/...xamples/designs/amaranth_driven_flow/amaranth_driven_flow/components/analogue/__init__.py
diff --git a/...examples/designs/amaranth_driven_flow/amaranth_driven_flow/components/digital/__init__.py b/...examples/designs/amaranth_driven_flow/amaranth_driven_flow/components/digital/__init__.py
diff --git a/...amples/designs/amaranth_driven_flow/amaranth_driven_flow/components/photonics/__init__.py b/...amples/designs/amaranth_driven_flow/amaranth_driven_flow/components/photonics/__init__.py
diff --git a/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/models/__init__.py b/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/models/__init__.py
diff --git a/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/models/analogue/__init__.py b/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/models/analogue/__init__.py
diff --git a/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/models/frequency/__init__.py b/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/models/frequency/__init__.py
diff --git a/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/models/logic/__init__.py b/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/models/logic/__init__.py
diff --git a/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/models/physical/__init__.py b/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/models/physical/__init__.py
diff --git a/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/models/transient/__init__.py b/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/models/transient/__init__.py
diff --git a/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/photonic/__init__.py b/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/photonic/__init__.py
diff --git a/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/src/truth_table_module.v b/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/src/truth_table_module.v
@@ -0,0 +1,32 @@
+/* Generated by Yosys 0.38 (git sha1 543faed9c8c, clang++ 17.0.6 -fPIC -Os) */
+
+(* top =  1  *)
+(* generator = "Amaranth" *)
+module top(phase_map_out, detector_in);
+  reg \$auto$verilog_backend.cc:2334:dump_module$1  = 0;
+  (* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:84" *)
+  input [1:0] detector_in;
+  wire [1:0] detector_in;
+  (* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:88" *)
+  output [1:0] phase_map_out;
+  reg [1:0] phase_map_out;
+  always @* begin
+    if (\$auto$verilog_backend.cc:2334:dump_module$1 ) begin end
+    (* full_case = 32'd1 *)
+    (* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:114" *)
+    casez (detector_in)
+      /* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:117" */
+      2'h0:
+          phase_map_out = 2'h0;
+      /* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:117" */
+      2'h1:
+          phase_map_out = 2'h2;
+      /* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:117" */
+      2'h2:
+          phase_map_out = 2'h3;
+      /* src = "/home/daquintero/phd/piel/piel/tools/amaranth/construct.py:117" */
+      2'h3:
+          phase_map_out = 2'h3;
+    endcase
+  end
+endmodule
diff --git a/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/tb/__init__.py b/docs/examples/designs/amaranth_driven_flow/amaranth_driven_flow/tb/__init__.py
diff --git a/docs/examples/designs/amaranth_driven_flow/docs/README.md b/docs/examples/designs/amaranth_driven_flow/docs/README.md
@@ -0,0 +1 @@
+amaranth_driven_flow
diff --git a/docs/examples/designs/amaranth_driven_flow/setup.py b/docs/examples/designs/amaranth_driven_flow/setup.py
@@ -0,0 +1,11 @@
+#!/usr/bin/env python 
+from distutils.core import setup 
+
+setup(name="amaranth_driven_flow", 
+	version="0.0.1", 
+	description="Example empty piel project."
+,	author="Dario Quintero", 
+	author_email="[email protected]", 
+	url="https://github.com/daquintero/piel", 
+	packages=['amaranth_driven_flow'], 
+)
diff --git a/docs/examples/designs/inverter/docs/README.md b/docs/examples/designs/inverter/docs/README.md
@@ -0,0 +1 @@
+inverter
diff --git a/docs/examples/designs/inverter/inverter/analogue/__init__.py b/docs/examples/designs/inverter/inverter/analogue/__init__.py
diff --git a/docs/examples/designs/inverter/inverter/components/__init__.py b/docs/examples/designs/inverter/inverter/components/__init__.py
diff --git a/docs/examples/designs/inverter/inverter/components/analogue/__init__.py b/docs/examples/designs/inverter/inverter/components/analogue/__init__.py
diff --git a/docs/examples/designs/inverter/inverter/components/digital/__init__.py b/docs/examples/designs/inverter/inverter/components/digital/__init__.py
diff --git a/docs/examples/designs/inverter/inverter/components/photonics/__init__.py b/docs/examples/designs/inverter/inverter/components/photonics/__init__.py
diff --git a/docs/examples/designs/inverter/inverter/config.json b/docs/examples/designs/inverter/inverter/config.json
@@ -0,0 +1,46 @@
+{
+    "meta": {
+        "version": 2,
+        "flow": [
+            "Yosys.Synthesis",
+            "OpenROAD.CheckSDCFiles",
+            "OpenROAD.Floorplan",
+            "OpenROAD.TapEndcapInsertion",
+            "OpenROAD.GeneratePDN",
+            "OpenROAD.IOPlacement",
+            "OpenROAD.GlobalPlacement",
+            "OpenROAD.RepairDesign",
+            "OpenROAD.DetailedPlacement",
+            "OpenROAD.GlobalRouting",
+            "OpenROAD.DetailedRouting",
+            "OpenROAD.FillInsertion",
+            "Magic.StreamOut",
+            "Magic.DRC",
+            "Checker.MagicDRC",
+            "Magic.SpiceExtraction",
+            "Netgen.LVS",
+            "Checker.LVS"
+        ]
+    },
+    "DESIGN_NAME": "inverter",
+    "VERILOG_FILES": "dir::src/*.v",
+    "CLOCK_PORT": null,
+    "FP_SIZING": "absolute",
+    "DIE_AREA": [
+        0,
+        0,
+        50,
+        50
+    ],
+    "PL_TARGET_DENSITY": 0.75,
+    "FP_PDN_AUTO_ADJUST": false,
+    "FP_PDN_VPITCH": 25,
+    "FP_PDN_HPITCH": 25,
+    "FP_PDN_VOFFSET": 5,
+    "FP_PDN_HOFFSET": 5,
+    "//": "With those two defined, the repair design step should do nothing:",
+    "RSZ_DONT_TOUCH_RX": "^in$",
+    "RSZ_DONT_TOUCH_LIST": [
+        "out"
+    ]
+}
diff --git a/docs/examples/designs/inverter/inverter/models/__init__.py b/docs/examples/designs/inverter/inverter/models/__init__.py
diff --git a/docs/examples/designs/inverter/inverter/models/analogue/__init__.py b/docs/examples/designs/inverter/inverter/models/analogue/__init__.py
diff --git a/docs/examples/designs/inverter/inverter/models/frequency/__init__.py b/docs/examples/designs/inverter/inverter/models/frequency/__init__.py
diff --git a/docs/examples/designs/inverter/inverter/models/logic/__init__.py b/docs/examples/designs/inverter/inverter/models/logic/__init__.py
diff --git a/docs/examples/designs/inverter/inverter/models/physical/__init__.py b/docs/examples/designs/inverter/inverter/models/physical/__init__.py
diff --git a/docs/examples/designs/inverter/inverter/models/transient/__init__.py b/docs/examples/designs/inverter/inverter/models/transient/__init__.py
diff --git a/docs/examples/designs/inverter/inverter/photonic/__init__.py b/docs/examples/designs/inverter/inverter/photonic/__init__.py
diff --git a/docs/examples/designs/inverter/inverter/src/inverter.v b/docs/examples/designs/inverter/inverter/src/inverter.v
@@ -0,0 +1,22 @@
+// Copyright 2020 Matt Venn
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+`default_nettype none
+module inverter (
+    input wire in,
+    output out );
+
+    assign out = !in;
+
+endmodule
diff --git a/docs/examples/designs/inverter/inverter/tb/__init__.py b/docs/examples/designs/inverter/inverter/tb/__init__.py
diff --git a/docs/examples/designs/inverter/setup.py b/docs/examples/designs/inverter/setup.py
@@ -0,0 +1,11 @@
+#!/usr/bin/env python 
+from distutils.core import setup 
+
+setup(name="inverter", 
+	version="0.0.1", 
+	description="Example empty piel project."
+,	author="Dario Quintero", 
+	author_email="[email protected]", 
+	url="https://github.com/daquintero/piel", 
+	packages=['inverter'], 
+)
diff --git a/docs/examples/designs/inverter1/config.json b/docs/examples/designs/inverter1/config.json
@@ -0,0 +1,46 @@
+{
+    "meta": {
+        "version": 2,
+        "flow": [
+            "Yosys.Synthesis",
+            "OpenROAD.CheckSDCFiles",
+            "OpenROAD.Floorplan",
+            "OpenROAD.TapEndcapInsertion",
+            "OpenROAD.GeneratePDN",
+            "OpenROAD.IOPlacement",
+            "OpenROAD.GlobalPlacement",
+            "OpenROAD.RepairDesign",
+            "OpenROAD.DetailedPlacement",
+            "OpenROAD.GlobalRouting",
+            "OpenROAD.DetailedRouting",
+            "OpenROAD.FillInsertion",
+            "Magic.StreamOut",
+            "Magic.DRC",
+            "Checker.MagicDRC",
+            "Magic.SpiceExtraction",
+            "Netgen.LVS",
+            "Checker.LVS"
+        ]
+    },
+    "DESIGN_NAME": "inverter",
+    "VERILOG_FILES": "dir::src/*.v",
+    "CLOCK_PORT": null,
+    "FP_SIZING": "absolute",
+    "DIE_AREA": [
+        0,
+        0,
+        50,
+        50
+    ],
+    "PL_TARGET_DENSITY": 0.75,
+    "FP_PDN_AUTO_ADJUST": false,
+    "FP_PDN_VPITCH": 25,
+    "FP_PDN_HPITCH": 25,
+    "FP_PDN_VOFFSET": 5,
+    "FP_PDN_HOFFSET": 5,
+    "//": "With those two defined, the repair design step should do nothing:",
+    "RSZ_DONT_TOUCH_RX": "^in$",
+    "RSZ_DONT_TOUCH_LIST": [
+        "out"
+    ]
+}