🚀 Initial refactor with dependency upgrades

daquintero · Jun 8, 2024 · cdf6f22 · cdf6f22
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diff --git a/...atic/img/examples/03a_sax_active_cosimulation/simple_ideal_o3_mzi_2x2_plots.PNG b/...atic/img/examples/03a_sax_active_cosimulation/simple_ideal_o3_mzi_2x2_plots.PNG
diff --git a/...atic/img/examples/03a_sax_active_cosimulation/simple_ideal_o4_mzi_2x2_plots.PNG b/...atic/img/examples/03a_sax_active_cosimulation/simple_ideal_o4_mzi_2x2_plots.PNG
diff --git a/...c/img/examples/03a_sax_active_cosimulation/switch_lattice_simulation_plot_0.PNG b/...c/img/examples/03a_sax_active_cosimulation/switch_lattice_simulation_plot_0.PNG
diff --git a/...c/img/examples/03a_sax_active_cosimulation/switch_lattice_simulation_plot_1.PNG b/...c/img/examples/03a_sax_active_cosimulation/switch_lattice_simulation_plot_1.PNG
diff --git a/...c/img/examples/03a_sax_active_cosimulation/switch_lattice_simulation_plot_2.PNG b/...c/img/examples/03a_sax_active_cosimulation/switch_lattice_simulation_plot_2.PNG
diff --git a/...c/img/examples/03a_sax_active_cosimulation/switch_lattice_simulation_plot_3.PNG b/...c/img/examples/03a_sax_active_cosimulation/switch_lattice_simulation_plot_3.PNG
diff --git a/docs/_static/img/examples/04_spice_cosimulation/linear_phase_power_mapping.png b/docs/_static/img/examples/04_spice_cosimulation/linear_phase_power_mapping.png
diff --git a/docs/_static/img/examples/04_spice_cosimulation/simple_energy_consumed_plot.PNG b/docs/_static/img/examples/04_spice_cosimulation/simple_energy_consumed_plot.PNG
diff --git a/docs/_static/img/examples/04_spice_cosimulation/simple_ideal_o3_mzi_2x2_plots.PNG b/docs/_static/img/examples/04_spice_cosimulation/simple_ideal_o3_mzi_2x2_plots.PNG
diff --git a/docs/_static/img/examples/04_spice_cosimulation/simple_ideal_o4_mzi_2x2_plots.PNG b/docs/_static/img/examples/04_spice_cosimulation/simple_ideal_o4_mzi_2x2_plots.PNG
diff --git a/docs/_static/img/examples/04_spice_cosimulation/simple_transient_plot.PNG b/docs/_static/img/examples/04_spice_cosimulation/simple_transient_plot.PNG
diff --git a/docs/_static/img/examples/04_spice_cosimulation/simple_transient_plot_full.PNG b/docs/_static/img/examples/04_spice_cosimulation/simple_transient_plot_full.PNG
diff --git a/...c/img/examples/04_spice_cosimulation/simple_transient_plot_power_resistance.PNG b/...c/img/examples/04_spice_cosimulation/simple_transient_plot_power_resistance.PNG
diff --git a/docs/examples/00_setup.py b/docs/examples/00_setup.py
@@ -1,6 +1,6 @@
 # # Project Setup Example
 
-# ## Enter Docker Environment
+# ## Within [IIC-OSIC-TOOLS](https://github.com/iic-jku/IIC-OSIC-TOOLS)
 #
 # We first enter the Docker environment by running:
 # ```

diff --git a/docs/examples/01_run_openlane_flow.py b/docs/examples/01_run_openlane_flow.py
@@ -301,6 +301,7 @@
     design_directory=amaranth_driven_flow,
     only_generate_flow_setup=True,
 )
+# TODO fix warnings
 
 # This should generate a `openlane 2` driven layout in the `amaranth_driven_flow` directory if you change the `only_generate_configuration` flag to `True`. Let's list the available runs in this project:
 

diff --git a/docs/examples/02_digital_design_simulation/02_digital_design_simulation.py b/docs/examples/02_digital_design_simulation/02_digital_design_simulation.py
@@ -152,12 +152,13 @@
 )
 # -
 
-# ## `cocoTb` Simulation
+# ## `cocotb` Simulation
 
 # It is strongly encouraged to get familiar with the `piel` flow project structure, as this file directory distribution enables the easy use between multiple design tools without conflicts or without structured organisation.
 
 # Location of our output files
 
+design_directory = piel.return_path(simple_design)
 source_output_files_directory = (
     piel.get_module_folder_type_location(
         module=simple_design, folder_type="digital_source"
@@ -189,6 +190,19 @@
     design_sources_list=list((design_directory / "src").iterdir()),
 )
 
+# ```shell
+# # #!/bin/bash
+# # Makefile
+# SIM ?= icarus
+# TOPLEVEL_LANG ?= verilog
+# VERILOG_SOURCES += /home/daquintero/phd/piel/docs/examples/designs/simple_design/simple_design/src/adder.vhdl
+# VERILOG_SOURCES += /home/daquintero/phd/piel/docs/examples/designs/simple_design/simple_design/src/adder.sv
+# TOPLEVEL := adder
+# MODULE := test_adder
+# include $(shell cocotb-config --makefiles)/Makefile.sim
+# PosixPath('/home/daquintero/phd/piel_private/docs/examples/designs/simple_design/simple_design/tb/Makefile')
+# ```
+
 # Now we can create the simulation output files from the `makefile`. Note this will only work in our configured Linux environment.
 
 # Run cocotb simulation
@@ -224,6 +238,7 @@
 # Now we can plot the corresponding data using the built-in interactive `bokeh` signal analyser function:
 
 piel.simple_plot_simulation_data(example_simple_simulation_data)
+# TODO fix this properly.
 
 # This looks like this:
 

diff --git a/docs/examples/02_digital_design_simulation/our_truth_table_module.v b/docs/examples/02_digital_design_simulation/our_truth_table_module.v
@@ -1,31 +1,30 @@
-/* Generated by Yosys 0.30+48 (git sha1 14d50a176d5, clang++ 11.1.0 -fPIC -Os) */
+/* Generated by Amaranth Yosys 0.40 (PyPI ver 0.40.0.0.post95, git sha1 a1bb0255d) */
 
-(* \amaranth.hierarchy  = "top" *)
 (* top =  1  *)
 (* generator = "Amaranth" *)
 module top(phase_map_out, detector_in);
-  reg \$auto$verilog_backend.cc:2097:dump_module$1  = 0;
-  (* src = "/home/daquintero/piel/piel/tools/amaranth/construct.py:43" *)
+  reg \$auto$verilog_backend.cc:2352:dump_module$1  = 0;
+  (* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:47" *)
   input [1:0] detector_in;
   wire [1:0] detector_in;
-  (* src = "/home/daquintero/piel/piel/tools/amaranth/construct.py:43" *)
+  (* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:47" *)
   output [1:0] phase_map_out;
   reg [1:0] phase_map_out;
   always @* begin
-    if (\$auto$verilog_backend.cc:2097:dump_module$1 ) begin end
+    if (\$auto$verilog_backend.cc:2352:dump_module$1 ) begin end
     (* full_case = 32'd1 *)
-    (* src = "/home/daquintero/piel/piel/tools/amaranth/construct.py:57" *)
+    (* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:61" *)
     casez (detector_in)
-      /* src = "/home/daquintero/piel/piel/tools/amaranth/construct.py:60" */
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
       2'h0:
           phase_map_out = 2'h0;
-      /* src = "/home/daquintero/piel/piel/tools/amaranth/construct.py:60" */
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
       2'h1:
           phase_map_out = 2'h2;
-      /* src = "/home/daquintero/piel/piel/tools/amaranth/construct.py:60" */
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
       2'h2:
           phase_map_out = 2'h3;
-      /* src = "/home/daquintero/piel/piel/tools/amaranth/construct.py:60" */
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
       2'h3:
           phase_map_out = 2'h3;
     endcase

diff --git a/docs/examples/02_digital_design_simulation/our_truth_table_module.vcd b/docs/examples/02_digital_design_simulation/our_truth_table_module.vcd
@@ -1,10 +1,10 @@
 $comment Generated by Amaranth $end
-$date 2023-08-25 09:34:27.507234 $end
+$date 2024-06-06 15:46:07.081849 $end
 $timescale 1 ps $end
 $scope module bench $end
 $scope module top $end
-$var wire 2 ! phase_map_out $end
-$var wire 2 " detector_in $end
+$var wire 2 ! detector_in $end
+$var wire 2 " phase_map_out $end
 $upscope $end
 $upscope $end
 $enddefinitions $end
@@ -14,11 +14,11 @@ b0 !
 b0 "
 $end
 #1000000
-b1 "
-b10 !
-#2000000
 b10 "
-b11 !
-#3000000
+b1 !
+#2000000
 b11 "
+b10 !
+#3000000
+b11 !
 #4000000
diff --git a/docs/examples/02a_large_scale_digital_layout/parallel/parallel_0/docs/README.md b/docs/examples/02a_large_scale_digital_layout/parallel/parallel_0/docs/README.md
@@ -0,0 +1 @@
+parallel_0
diff --git a/docs/examples/02a_large_scale_digital_layout/parallel/parallel_0/parallel_0/__init__.py b/docs/examples/02a_large_scale_digital_layout/parallel/parallel_0/parallel_0/__init__.py
diff --git a/...amples/02a_large_scale_digital_layout/parallel/parallel_0/parallel_0/analogue/__init__.py b/...amples/02a_large_scale_digital_layout/parallel/parallel_0/parallel_0/analogue/__init__.py
diff --git a/...ples/02a_large_scale_digital_layout/parallel/parallel_0/parallel_0/components/__init__.py b/...ples/02a_large_scale_digital_layout/parallel/parallel_0/parallel_0/components/__init__.py
diff --git a/...large_scale_digital_layout/parallel/parallel_0/parallel_0/components/analogue/__init__.py b/...large_scale_digital_layout/parallel/parallel_0/parallel_0/components/analogue/__init__.py
diff --git a/..._large_scale_digital_layout/parallel/parallel_0/parallel_0/components/digital/__init__.py b/..._large_scale_digital_layout/parallel/parallel_0/parallel_0/components/digital/__init__.py
diff --git a/...arge_scale_digital_layout/parallel/parallel_0/parallel_0/components/photonics/__init__.py b/...arge_scale_digital_layout/parallel/parallel_0/parallel_0/components/photonics/__init__.py
diff --git a/...examples/02a_large_scale_digital_layout/parallel/parallel_0/parallel_0/models/__init__.py b/...examples/02a_large_scale_digital_layout/parallel/parallel_0/parallel_0/models/__init__.py
diff --git a/...02a_large_scale_digital_layout/parallel/parallel_0/parallel_0/models/analogue/__init__.py b/...02a_large_scale_digital_layout/parallel/parallel_0/parallel_0/models/analogue/__init__.py
diff --git a/...2a_large_scale_digital_layout/parallel/parallel_0/parallel_0/models/frequency/__init__.py b/...2a_large_scale_digital_layout/parallel/parallel_0/parallel_0/models/frequency/__init__.py
diff --git a/...es/02a_large_scale_digital_layout/parallel/parallel_0/parallel_0/models/logic/__init__.py b/...es/02a_large_scale_digital_layout/parallel/parallel_0/parallel_0/models/logic/__init__.py
diff --git a/...02a_large_scale_digital_layout/parallel/parallel_0/parallel_0/models/physical/__init__.py b/...02a_large_scale_digital_layout/parallel/parallel_0/parallel_0/models/physical/__init__.py
diff --git a/...2a_large_scale_digital_layout/parallel/parallel_0/parallel_0/models/transient/__init__.py b/...2a_large_scale_digital_layout/parallel/parallel_0/parallel_0/models/transient/__init__.py
diff --git a/...amples/02a_large_scale_digital_layout/parallel/parallel_0/parallel_0/photonic/__init__.py b/...amples/02a_large_scale_digital_layout/parallel/parallel_0/parallel_0/photonic/__init__.py
diff --git a/...2a_large_scale_digital_layout/parallel/parallel_0/parallel_0/src/our_truth_table_module.v b/...2a_large_scale_digital_layout/parallel/parallel_0/parallel_0/src/our_truth_table_module.v
@@ -0,0 +1,68 @@
+/* Generated by Yosys 0.38 (git sha1 543faed9c8c, clang++ 16.0.6 -fPIC -Os) */
+
+(* top =  1  *)
+(* generator = "Amaranth" *)
+module top(\output , \input );
+  reg \$auto$verilog_backend.cc:2334:dump_module$1  = 0;
+  (* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:47" *)
+  input [3:0] \input ;
+  wire [3:0] \input ;
+  (* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:47" *)
+  output [3:0] \output ;
+  reg [3:0] \output ;
+  always @* begin
+    if (\$auto$verilog_backend.cc:2334:dump_module$1 ) begin end
+    (* full_case = 32'd1 *)
+    (* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:61" *)
+    casez (\input )
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'h0:
+          \output  = 4'h5;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'h1:
+          \output  = 4'hc;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'h2:
+          \output  = 4'h5;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'h3:
+          \output  = 4'h6;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'h4:
+          \output  = 4'h2;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'h5:
+          \output  = 4'hd;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'h6:
+          \output  = 4'h6;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'h7:
+          \output  = 4'h3;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'h8:
+          \output  = 4'h9;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'h9:
+          \output  = 4'he;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'ha:
+          \output  = 4'h4;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'hb:
+          \output  = 4'h8;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'hc:
+          \output  = 4'h1;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'hd:
+          \output  = 4'hb;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'he:
+          \output  = 4'hf;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'hf:
+          \output  = 4'ha;
+    endcase
+  end
+endmodule
diff --git a/docs/examples/02a_large_scale_digital_layout/parallel/parallel_0/parallel_0/tb/__init__.py b/docs/examples/02a_large_scale_digital_layout/parallel/parallel_0/parallel_0/tb/__init__.py
diff --git a/docs/examples/02a_large_scale_digital_layout/parallel/parallel_0/setup.py b/docs/examples/02a_large_scale_digital_layout/parallel/parallel_0/setup.py
@@ -0,0 +1,12 @@
+#!/usr/bin/env python
+from distutils.core import setup
+
+setup(
+    name="parallel_0",
+    version="0.0.1",
+    description="Example empty piel project.",
+    author="Dario Quintero",
+    author_email="[email protected]",
+    url="https://github.com/daquintero/piel",
+    packages=["parallel_0"],
+)
diff --git a/docs/examples/02a_large_scale_digital_layout/parallel/parallel_1/docs/README.md b/docs/examples/02a_large_scale_digital_layout/parallel/parallel_1/docs/README.md
@@ -0,0 +1 @@
+parallel_1
diff --git a/docs/examples/02a_large_scale_digital_layout/parallel/parallel_1/parallel_1/__init__.py b/docs/examples/02a_large_scale_digital_layout/parallel/parallel_1/parallel_1/__init__.py
diff --git a/...amples/02a_large_scale_digital_layout/parallel/parallel_1/parallel_1/analogue/__init__.py b/...amples/02a_large_scale_digital_layout/parallel/parallel_1/parallel_1/analogue/__init__.py
diff --git a/...ples/02a_large_scale_digital_layout/parallel/parallel_1/parallel_1/components/__init__.py b/...ples/02a_large_scale_digital_layout/parallel/parallel_1/parallel_1/components/__init__.py
diff --git a/...large_scale_digital_layout/parallel/parallel_1/parallel_1/components/analogue/__init__.py b/...large_scale_digital_layout/parallel/parallel_1/parallel_1/components/analogue/__init__.py
diff --git a/..._large_scale_digital_layout/parallel/parallel_1/parallel_1/components/digital/__init__.py b/..._large_scale_digital_layout/parallel/parallel_1/parallel_1/components/digital/__init__.py
diff --git a/...arge_scale_digital_layout/parallel/parallel_1/parallel_1/components/photonics/__init__.py b/...arge_scale_digital_layout/parallel/parallel_1/parallel_1/components/photonics/__init__.py
diff --git a/...examples/02a_large_scale_digital_layout/parallel/parallel_1/parallel_1/models/__init__.py b/...examples/02a_large_scale_digital_layout/parallel/parallel_1/parallel_1/models/__init__.py
diff --git a/...02a_large_scale_digital_layout/parallel/parallel_1/parallel_1/models/analogue/__init__.py b/...02a_large_scale_digital_layout/parallel/parallel_1/parallel_1/models/analogue/__init__.py
diff --git a/...2a_large_scale_digital_layout/parallel/parallel_1/parallel_1/models/frequency/__init__.py b/...2a_large_scale_digital_layout/parallel/parallel_1/parallel_1/models/frequency/__init__.py
diff --git a/...es/02a_large_scale_digital_layout/parallel/parallel_1/parallel_1/models/logic/__init__.py b/...es/02a_large_scale_digital_layout/parallel/parallel_1/parallel_1/models/logic/__init__.py
diff --git a/...02a_large_scale_digital_layout/parallel/parallel_1/parallel_1/models/physical/__init__.py b/...02a_large_scale_digital_layout/parallel/parallel_1/parallel_1/models/physical/__init__.py
diff --git a/...2a_large_scale_digital_layout/parallel/parallel_1/parallel_1/models/transient/__init__.py b/...2a_large_scale_digital_layout/parallel/parallel_1/parallel_1/models/transient/__init__.py
diff --git a/...amples/02a_large_scale_digital_layout/parallel/parallel_1/parallel_1/photonic/__init__.py b/...amples/02a_large_scale_digital_layout/parallel/parallel_1/parallel_1/photonic/__init__.py
diff --git a/...2a_large_scale_digital_layout/parallel/parallel_1/parallel_1/src/our_truth_table_module.v b/...2a_large_scale_digital_layout/parallel/parallel_1/parallel_1/src/our_truth_table_module.v
@@ -0,0 +1,68 @@
+/* Generated by Yosys 0.38 (git sha1 543faed9c8c, clang++ 16.0.6 -fPIC -Os) */
+
+(* top =  1  *)
+(* generator = "Amaranth" *)
+module top(\output , \input );
+  reg \$auto$verilog_backend.cc:2334:dump_module$1  = 0;
+  (* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:47" *)
+  input [3:0] \input ;
+  wire [3:0] \input ;
+  (* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:47" *)
+  output [3:0] \output ;
+  reg [3:0] \output ;
+  always @* begin
+    if (\$auto$verilog_backend.cc:2334:dump_module$1 ) begin end
+    (* full_case = 32'd1 *)
+    (* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:61" *)
+    casez (\input )
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'h0:
+          \output  = 4'h5;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'h1:
+          \output  = 4'hc;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'h2:
+          \output  = 4'h5;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'h3:
+          \output  = 4'h6;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'h4:
+          \output  = 4'h2;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'h5:
+          \output  = 4'hd;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'h6:
+          \output  = 4'h6;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'h7:
+          \output  = 4'h3;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'h8:
+          \output  = 4'h9;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'h9:
+          \output  = 4'he;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'ha:
+          \output  = 4'h4;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'hb:
+          \output  = 4'h8;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'hc:
+          \output  = 4'h1;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'hd:
+          \output  = 4'hb;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'he:
+          \output  = 4'hf;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'hf:
+          \output  = 4'ha;
+    endcase
+  end
+endmodule
diff --git a/docs/examples/02a_large_scale_digital_layout/parallel/parallel_1/parallel_1/tb/__init__.py b/docs/examples/02a_large_scale_digital_layout/parallel/parallel_1/parallel_1/tb/__init__.py
diff --git a/docs/examples/02a_large_scale_digital_layout/parallel/parallel_1/setup.py b/docs/examples/02a_large_scale_digital_layout/parallel/parallel_1/setup.py
@@ -0,0 +1,12 @@
+#!/usr/bin/env python
+from distutils.core import setup
+
+setup(
+    name="parallel_1",
+    version="0.0.1",
+    description="Example empty piel project.",
+    author="Dario Quintero",
+    author_email="[email protected]",
+    url="https://github.com/daquintero/piel",
+    packages=["parallel_1"],
+)
diff --git a/docs/examples/02a_large_scale_digital_layout/parallel/parallel_2/docs/README.md b/docs/examples/02a_large_scale_digital_layout/parallel/parallel_2/docs/README.md
@@ -0,0 +1 @@
+parallel_2
diff --git a/docs/examples/02a_large_scale_digital_layout/parallel/parallel_2/parallel_2/__init__.py b/docs/examples/02a_large_scale_digital_layout/parallel/parallel_2/parallel_2/__init__.py
diff --git a/...amples/02a_large_scale_digital_layout/parallel/parallel_2/parallel_2/analogue/__init__.py b/...amples/02a_large_scale_digital_layout/parallel/parallel_2/parallel_2/analogue/__init__.py
diff --git a/...ples/02a_large_scale_digital_layout/parallel/parallel_2/parallel_2/components/__init__.py b/...ples/02a_large_scale_digital_layout/parallel/parallel_2/parallel_2/components/__init__.py
diff --git a/...large_scale_digital_layout/parallel/parallel_2/parallel_2/components/analogue/__init__.py b/...large_scale_digital_layout/parallel/parallel_2/parallel_2/components/analogue/__init__.py
diff --git a/..._large_scale_digital_layout/parallel/parallel_2/parallel_2/components/digital/__init__.py b/..._large_scale_digital_layout/parallel/parallel_2/parallel_2/components/digital/__init__.py
diff --git a/...arge_scale_digital_layout/parallel/parallel_2/parallel_2/components/photonics/__init__.py b/...arge_scale_digital_layout/parallel/parallel_2/parallel_2/components/photonics/__init__.py
diff --git a/...examples/02a_large_scale_digital_layout/parallel/parallel_2/parallel_2/models/__init__.py b/...examples/02a_large_scale_digital_layout/parallel/parallel_2/parallel_2/models/__init__.py
diff --git a/...02a_large_scale_digital_layout/parallel/parallel_2/parallel_2/models/analogue/__init__.py b/...02a_large_scale_digital_layout/parallel/parallel_2/parallel_2/models/analogue/__init__.py
diff --git a/...2a_large_scale_digital_layout/parallel/parallel_2/parallel_2/models/frequency/__init__.py b/...2a_large_scale_digital_layout/parallel/parallel_2/parallel_2/models/frequency/__init__.py
diff --git a/...es/02a_large_scale_digital_layout/parallel/parallel_2/parallel_2/models/logic/__init__.py b/...es/02a_large_scale_digital_layout/parallel/parallel_2/parallel_2/models/logic/__init__.py
diff --git a/...02a_large_scale_digital_layout/parallel/parallel_2/parallel_2/models/physical/__init__.py b/...02a_large_scale_digital_layout/parallel/parallel_2/parallel_2/models/physical/__init__.py
diff --git a/...2a_large_scale_digital_layout/parallel/parallel_2/parallel_2/models/transient/__init__.py b/...2a_large_scale_digital_layout/parallel/parallel_2/parallel_2/models/transient/__init__.py
diff --git a/...amples/02a_large_scale_digital_layout/parallel/parallel_2/parallel_2/photonic/__init__.py b/...amples/02a_large_scale_digital_layout/parallel/parallel_2/parallel_2/photonic/__init__.py
diff --git a/...2a_large_scale_digital_layout/parallel/parallel_2/parallel_2/src/our_truth_table_module.v b/...2a_large_scale_digital_layout/parallel/parallel_2/parallel_2/src/our_truth_table_module.v
@@ -0,0 +1,68 @@
+/* Generated by Yosys 0.38 (git sha1 543faed9c8c, clang++ 16.0.6 -fPIC -Os) */
+
+(* top =  1  *)
+(* generator = "Amaranth" *)
+module top(\output , \input );
+  reg \$auto$verilog_backend.cc:2334:dump_module$1  = 0;
+  (* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:47" *)
+  input [3:0] \input ;
+  wire [3:0] \input ;
+  (* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:47" *)
+  output [3:0] \output ;
+  reg [3:0] \output ;
+  always @* begin
+    if (\$auto$verilog_backend.cc:2334:dump_module$1 ) begin end
+    (* full_case = 32'd1 *)
+    (* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:61" *)
+    casez (\input )
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'h0:
+          \output  = 4'h5;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'h1:
+          \output  = 4'hc;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'h2:
+          \output  = 4'h5;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'h3:
+          \output  = 4'h6;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'h4:
+          \output  = 4'h2;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'h5:
+          \output  = 4'hd;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'h6:
+          \output  = 4'h6;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'h7:
+          \output  = 4'h3;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'h8:
+          \output  = 4'h9;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'h9:
+          \output  = 4'he;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'ha:
+          \output  = 4'h4;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'hb:
+          \output  = 4'h8;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'hc:
+          \output  = 4'h1;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'hd:
+          \output  = 4'hb;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'he:
+          \output  = 4'hf;
+      /* src = "/home/daquintero/phd/piel_private/piel/tools/amaranth/construct.py:64" */
+      4'hf:
+          \output  = 4'ha;
+    endcase
+  end
+endmodule
diff --git a/docs/examples/02a_large_scale_digital_layout/parallel/parallel_2/parallel_2/tb/__init__.py b/docs/examples/02a_large_scale_digital_layout/parallel/parallel_2/parallel_2/tb/__init__.py
diff --git a/docs/examples/02a_large_scale_digital_layout/parallel/parallel_2/setup.py b/docs/examples/02a_large_scale_digital_layout/parallel/parallel_2/setup.py
@@ -0,0 +1,12 @@
+#!/usr/bin/env python
+from distutils.core import setup
+
+setup(
+    name="parallel_2",
+    version="0.0.1",
+    description="Example empty piel project.",
+    author="Dario Quintero",
+    author_email="[email protected]",
+    url="https://github.com/daquintero/piel",
+    packages=["parallel_2"],
+)
diff --git a/docs/examples/02a_large_scale_digital_layout/parallel/parallel_3/docs/README.md b/docs/examples/02a_large_scale_digital_layout/parallel/parallel_3/docs/README.md
@@ -0,0 +1 @@
+parallel_3
diff --git a/docs/examples/02a_large_scale_digital_layout/parallel/parallel_3/parallel_3/__init__.py b/docs/examples/02a_large_scale_digital_layout/parallel/parallel_3/parallel_3/__init__.py
diff --git a/...amples/02a_large_scale_digital_layout/parallel/parallel_3/parallel_3/analogue/__init__.py b/...amples/02a_large_scale_digital_layout/parallel/parallel_3/parallel_3/analogue/__init__.py
diff --git a/...ples/02a_large_scale_digital_layout/parallel/parallel_3/parallel_3/components/__init__.py b/...ples/02a_large_scale_digital_layout/parallel/parallel_3/parallel_3/components/__init__.py
diff --git a/...large_scale_digital_layout/parallel/parallel_3/parallel_3/components/analogue/__init__.py b/...large_scale_digital_layout/parallel/parallel_3/parallel_3/components/analogue/__init__.py
diff --git a/..._large_scale_digital_layout/parallel/parallel_3/parallel_3/components/digital/__init__.py b/..._large_scale_digital_layout/parallel/parallel_3/parallel_3/components/digital/__init__.py
diff --git a/...arge_scale_digital_layout/parallel/parallel_3/parallel_3/components/photonics/__init__.py b/...arge_scale_digital_layout/parallel/parallel_3/parallel_3/components/photonics/__init__.py
diff --git a/...examples/02a_large_scale_digital_layout/parallel/parallel_3/parallel_3/models/__init__.py b/...examples/02a_large_scale_digital_layout/parallel/parallel_3/parallel_3/models/__init__.py
diff --git a/...02a_large_scale_digital_layout/parallel/parallel_3/parallel_3/models/analogue/__init__.py b/...02a_large_scale_digital_layout/parallel/parallel_3/parallel_3/models/analogue/__init__.py
diff --git a/...2a_large_scale_digital_layout/parallel/parallel_3/parallel_3/models/frequency/__init__.py b/...2a_large_scale_digital_layout/parallel/parallel_3/parallel_3/models/frequency/__init__.py
diff --git a/...es/02a_large_scale_digital_layout/parallel/parallel_3/parallel_3/models/logic/__init__.py b/...es/02a_large_scale_digital_layout/parallel/parallel_3/parallel_3/models/logic/__init__.py
diff --git a/...02a_large_scale_digital_layout/parallel/parallel_3/parallel_3/models/physical/__init__.py b/...02a_large_scale_digital_layout/parallel/parallel_3/parallel_3/models/physical/__init__.py
diff --git a/...2a_large_scale_digital_layout/parallel/parallel_3/parallel_3/models/transient/__init__.py b/...2a_large_scale_digital_layout/parallel/parallel_3/parallel_3/models/transient/__init__.py
diff --git a/...amples/02a_large_scale_digital_layout/parallel/parallel_3/parallel_3/photonic/__init__.py b/...amples/02a_large_scale_digital_layout/parallel/parallel_3/parallel_3/photonic/__init__.py