Merge pull request #1495 from diffblue/multiple_instances1

Verilog: test for gate instantiation with multiple instances

Author: tautschnig

regression/verilog/primitive_gates/multiple_instances1.desc

@@ -0,0 +1,8 @@
+CORE
+multiple_instances1.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--

regression/verilog/primitive_gates/multiple_instances1.sv

@@ -0,0 +1,10 @@
+module main;
+
+  wire w1, w2;
+
+  and a1(w1, 1, 1), a2(w2, 1, 0);
+
+  initial assert(w1==1);
+  initial assert(w2==0);
+
+endmodule