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Pull requests list

netlists can now track properties with arbitrary shapes engines
#1052 opened Apr 4, 2025 by kroening • Draft
SMV netlist: translate some SVA to LTL engines
#1051 opened Apr 4, 2025 by kroening • Draft
SVA: sequence property expressions Verilog
#1049 opened Mar 31, 2025 by kroening • Draft
Verilog: type for SVA sequences Verilog
#1041 opened Mar 28, 2025 by kroening Loading…
SMV: expression typechecker now post-traversal SMV
#1040 opened Mar 28, 2025 by kroening Loading…
2
SVA monitor engines Verilog
#1011 opened Feb 25, 2025 by kroening • Draft
SystemVerilog: --initial-zero Verilog
#1001 opened Feb 20, 2025 by kroening Loading…
2
SystemVerilog: interface instantiation Verilog
#972 opened Feb 6, 2025 by kroening • Draft
SystemVerilog: declarations in named blocks in tasks/functions Verilog
#970 opened Feb 6, 2025 by kroening • Draft
1
SystemVerilog: preserve scopes between compilation units Verilog
#963 opened Feb 4, 2025 by kroening • Draft
SystemVerilog: create identifier expressions in scanner Verilog
#953 opened Jan 29, 2025 by kroening • Draft
Add chipsalliance/sv-tests to CI
#939 opened Jan 17, 2025 by kroening • Draft
aval/bval lowering for reduction operators Verilog
#930 opened Jan 16, 2025 by kroening • Draft
vlindex: fix parsing for constraint_block
#924 opened Jan 6, 2025 by kroening • Draft
SystemVerilog: fix identifier on enum type Verilog
#919 opened Jan 2, 2025 by kroening • Draft
liveness engine engines
#915 opened Dec 29, 2024 by kroening • Draft
SMV: clean up parse tree SMV
#909 opened Dec 27, 2024 by kroening • Draft
SMV: typechecking for ?: SMV
#906 opened Dec 26, 2024 by kroening • Draft
SMV: typechecking for unary minus SMV
#893 opened Dec 20, 2024 by kroening • Draft
SystemVerilog: type parameter ports Verilog
#842 opened Nov 21, 2024 by kroening • Draft
SVA/LTL property instrumentation engines
#797 opened Nov 3, 2024 by kroening • Draft
Verilog: use zero_extend_exprt Verilog
#796 opened Nov 1, 2024 by kroening • Draft
word-level BMC: add missing SVA expressions Verilog
#759 opened Oct 9, 2024 by kroening • Draft
Verilog: default aval/bval lowering Verilog
#668 opened Sep 5, 2024 by kroening • Draft
Verilog: expr2verilog can now decode aval/bval constants Verilog
#570 opened Jun 22, 2024 by kroening • Draft
ProTip! Updated in the last three days: updated:>2025-04-03.