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Update SVE instructions that writes to GC regs #112389

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Feb 12, 2025
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Update SVE instructions that writes to GC regs #112389

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16 changes: 16 additions & 0 deletions src/coreclr/jit/emitarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1087,6 +1087,22 @@ bool emitter::emitInsMayWriteToGCReg(instrDesc* id)
case IF_SR_1A: // SR_1A ................ ...........ttttt Rt (dc zva, mrs)
return ins == INS_mrs_tpid0;

// Below SVE instructions write to GPR and hence GC reg
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How did you figure out this list? Just want to make sure we've got all of them

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I just went through the instrsarm64sve.h and went over the instructions that has GPR as destination register and added them to this list.

case IF_SVE_CO_3A: // clasta, clastb
case IF_SVE_BM_1A: // decb, decd, dech, decw, incb, incd, inch, incw
case IF_SVE_BO_1A: // sqdecb, sqdecd, sqdech, sqdecw, sqincb, sqincd, sqinch, sqincw, uqdecb, uqdecd, uqdech,
// uqdecw, uqincb, uqincd, uqinch, uqincw
case IF_SVE_CS_3A: // lasta, lastb
case IF_SVE_DK_3A: // cntp
case IF_SVE_DL_2A: // cntp
case IF_SVE_DM_2A: // decp, incp
case IF_SVE_DO_2A: // sqdecp, sqincp, uqdecp, uqincp
case IF_SVE_BB_2A: // addpl, addvl
case IF_SVE_BC_1A: // rdvl
case IF_SVE_BL_1A: // cntb, cntd, cnth, cntw
case IF_SVE_DS_2A: // ctermeq, ctermne
return true;

default:
return false;
}
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