Add uvm testbenchs

.github/workflows/uvm_ci.yaml

@@ -0,0 +1,26 @@
+name: Run UVM tests
+
+on:
+  push: # This now triggers on pushes to any branch
+  pull_request: # This now triggers on pull requests to any branch
+
+jobs:
+  Extract-Buses:
+    runs-on: ubuntu-latest
+    outputs:
+      IPs: ${{ steps.set-IPs-matrix.outputs.IPs }}
+      buses: ${{ steps.extract_buses.outputs.buses }}
+    steps:
+      - name: Extract Supported Buses
+        id: extract_buses
+        uses: efabless/EF_UVM/.github/actions/get-bus@main
+      - name: Check Output
+        run: echo ${{ steps.extract_buses.outputs.buses }}
+  Run-IP-Tests:
+    uses: efabless/EF_UVM/.github/workflows/run_IP.yaml@main
+    needs: [Extract-Buses]
+    with:
+      test-names: "all_tests"
+      name: ${{ github.event.repository.name }}
+      buses: ${{ needs.Extract-Buses.outputs.buses }}
+      is-ip: true

EF_AES.yaml

@@ -76,25 +76,30 @@ ports:
 
 registers:
 - name: STATUS
-  size: 8
+  size: 3
   mode: r
   fifo: no
   offset: 0
   bit_access: no
-  description: "Status register bit 6: ready , bit 7: valid"
+  description: "Status register bit 0: valid, bit 1: ready, bit 2: key ready"
   fields:
+    - name: valid_reg
+      bit_offset: 0
+      bit_width: 1
+      read_port: result_valid
+      description: Result is valid
     - name: ready_reg
-      bit_offset: 6
+      bit_offset: 1
       bit_width: 1
       read_port: ready
       description: Ready to start
-    - name: valid_reg
-      bit_offset: 7
+    - name: key_ready_reg
+      bit_offset: 2
       bit_width: 1
-      read_port: result_valid
-      description: Result is valid
+      read_port: key_ready
+      description: Key is ready
 - name: CTRL
-  size: 8
+  size: 4
   mode: w
   fifo: no
   offset: 4
@@ -264,3 +269,6 @@ flags:
 - name: ready
   port: ready
   description: Ready to start
+- name: key_ready
+  port: key_ready
+  description: Key is ready

hdl/rtl/aes_core.v

@@ -53,7 +53,8 @@ module aes_core(
 
                 input wire [127 : 0]  block,
                 output wire [127 : 0] result,
-                output wire           result_valid
+                output wire           result_valid,
+                output wire           key_ready
                );
 
 
@@ -89,7 +90,6 @@ module aes_core(
   reg            init_state;
 
   wire [127 : 0] round_key;
-  wire           key_ready;
 
   reg            enc_next;
   wire [3 : 0]   enc_round_nr;