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Merge branch 'dev' into cts-options
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kareefardi authored Dec 11, 2024
2 parents 0bd11ce + df6079d commit f7ac225
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27 changes: 23 additions & 4 deletions Changelog.md
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Expand Up @@ -13,6 +13,25 @@
## API Breaks
## Documentation
-->

# 2.2.9

## Steps

* `Yosys.JsonHeader`, `Yosys.Synthesis`

* Fixed `VERILOG_INCLUDE_DIRS` being a list of strings instead of a list of
`Path`s.

# 2.2.8

## Steps

* `Checker.*Violations`

* Changed `TIMING_VIOLATION_CORNERS` to a PDK variable to avoid breaking PDKs
without `tt` in corner names.

# 2.2.7

## Steps
Expand All @@ -27,13 +46,13 @@

* `OpenROAD.ResizerTimingPostGRT`

* Fixed `GRT_RESIZER_GATE_CLONING` incorrectly applied to hold fixing instead
of setup fixing.
* Fixed `GRT_RESIZER_GATE_CLONING` incorrectly applied to hold fixing instead
of setup fixing.

* `OpenROAD.ResizerTimingPostCTS`

* Fixed `PL_RESIZER_GATE_CLONING` incorrectly applied to hold fixing instead
of setup fixing.
* Fixed `PL_RESIZER_GATE_CLONING` incorrectly applied to hold fixing instead
of setup fixing.

# 2.2.5

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1 change: 1 addition & 0 deletions openlane/config/pdk_compat.py
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Expand Up @@ -228,6 +228,7 @@ def process_sta(key: str):
]

new["DEFAULT_CORNER"] = f"nom_{default_pvt}"
new["TIMING_VIOLATION_CORNERS"] = ["*tt*"]
new["LIB"] = lib_sta

# x4. Constraints (sky130/gf180mcu)
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2 changes: 1 addition & 1 deletion openlane/steps/checker.py
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Expand Up @@ -464,7 +464,7 @@ def __init_subclass__(cls, **kwargs):
cls.base_corner_var_name,
List[str],
"A list of wildcards matching IPVT corners to use during checking for timing violations.",
default=["*tt*"],
pdk=True,
deprecated_names=["TIMING_VIOLATIONS_CORNERS"],
),
cls.get_corner_variable(),
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40 changes: 1 addition & 39 deletions openlane/steps/pyosys.py
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Expand Up @@ -28,44 +28,6 @@
from ..logging import debug, verbose
from ..common import Path, get_script_dir, process_list_file

verilog_rtl_cfg_vars = [
Variable(
"VERILOG_FILES",
List[Path],
"The paths of the design's Verilog files.",
),
Variable(
"VERILOG_DEFINES",
Optional[List[str]],
"Preprocessor defines for input Verilog files.",
deprecated_names=["SYNTH_DEFINES"],
),
Variable(
"VERILOG_POWER_DEFINE",
Optional[str],
"Specifies the name of the define used to guard power and ground connections in the input RTL.",
deprecated_names=["SYNTH_USE_PG_PINS_DEFINES", "SYNTH_POWER_DEFINE"],
default="USE_POWER_PINS",
),
Variable(
"VERILOG_INCLUDE_DIRS",
Optional[List[str]],
"Specifies the Verilog `include` directories.",
),
Variable(
"USE_SYNLIG",
bool,
"Use the Synlig plugin to process files, which has better SystemVerilog parsing capabilities but may not be compatible with all Yosys commands and attributes.",
default=False,
),
Variable(
"SYNLIG_DEFER",
bool,
"Uses -defer flag when reading files the Synlig plugin, which may improve performance by reading each file separately, but is experimental.",
default=False,
),
]

starts_with_whitespace = re.compile(r"^\s+.+$")

yosys_cell_rx = r"cell\s+\S+\s+\((\S+)\)"
Expand Down Expand Up @@ -149,7 +111,7 @@ def _parse_yosys_check(
),
Variable(
"VERILOG_INCLUDE_DIRS",
Optional[List[str]],
Optional[List[Path]],
"Specifies the Verilog `include` directories.",
),
Variable(
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2 changes: 1 addition & 1 deletion pyproject.toml
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@@ -1,6 +1,6 @@
[tool.poetry]
name = "openlane"
version = "2.2.7"
version = "2.2.9"
description = "An infrastructure for implementing chip design flows"
authors = ["Efabless Corporation and Contributors <[email protected]>"]
readme = "Readme.md"
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2 changes: 2 additions & 0 deletions test/steps/excluded_step_tests
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@@ -0,0 +1,2 @@
checker.holdviolations/004-success-hold-overwrite
checker.holdviolations/005-fail-different-corner

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