Indexing taking a significant amount of time

[vmirian1982]

After the initial open (36467 indexed objects), when I click on file 'A' to navigate, the SystemVerilog console shows "Auto Indexing: A". When I click on a symbol in file 'A' to retrieve its definition, the blue status bar shows up for approximately a minute, then the definition is shown in file 'B'. These latter steps where with default SystemVerilog extensions settings.

I updated the settings in hopes to improve the indexing performance. These are the settings in the workspace area for the extension:
"systemverilog.includeIndexing": [
"${workspaceFolder}/hdl/**/*.{sv,v,svh,vh,svp}"
]

Now, when I click on file 'A' (646 indexed objects) to navigate, the SystemVerilog console shows "Auto Indexing: A". When I click on a symbol in file 'A' to retrieve its definition, the blue status bar shows up for a few minutes, then dies.

Why does the indexing resume to 0 when the "systemverilog.includeIndexing" is set?

How can I optimize the performance of the indexing? Are there any recommendations?

Any helps would be appreciated. Thank you.

[vmirian1982]

A brief update: I recall other indexing service (e.g. Intellisense) having the same issue. It was solved by changing the location of the database. Is there a manner to change the location of the database?

[JendaPov]

I have similar issues, to summarize: indexing in a project workspace is so slow that its working well only inside 1 file. I have tried many things, but not successfully.

Lets start with probably one of the most important and also easiest ways how to deal with this issue (and also in general a must for any EDA tool): I tried to use the systemverilog.includeIndexing in this way: Add files only when in a specific workspace: /abs/path/to/workspace/rtl/**/*.{sv,v,svh,vh} . So, basically tried to misuse this as a RTL filelist (or a whitelist if you will). It hasnt really helped and moreover after a synthesis the extension started to dig into the new synthesized netlist on its own, which I found out from a message popping up that the netlist verilog file is too large.

Does systemverilog.includeIndexing actually really work as a whitelist? or its some additional list on top of the current workspace folders? Or is there any other way to do this?

Note: In (System)Verilog files I only see the VS Code built-in "text based" code completion, not any semantic one based on the indexed symbols. Is that expected or do I have some totally broken setup?

Thanks and regards