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34 Open 101 Closed
34 Open 101 Closed
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Issues list

Instances named as modules
#242 opened Sep 28, 2024 by arquer
Verilator problem matcher regex doesn't actually detect anything
#231 opened Jul 18, 2024 by alex-the-new-guy
3
systemverilog.maxLineCountIndexing issue
#228 opened Jun 12, 2024 by hubertdetartas
1
Go to definition doesn't work for "spi" module name
#227 opened May 31, 2024 by hi0t
1
Can an option be added to disable the custom icons?
#226 opened Apr 28, 2024 by dbarrie
2
Syntax highlighting error
#224 opened Feb 21, 2024 by bbsbucket
Toggle Line Comment not working for Verilog Filelist?
#223 opened Feb 15, 2024 by musketon-be
Feature request, input/output signals use different colors enhancement New feature or request
#221 opened Jan 21, 2024 by haimag
When instantiating, the signal can be listed in the form of wire
#220 opened Jan 19, 2024 by haidoph
1
SystemVerilog - Language Support - VCS linter
#201 opened Aug 14, 2023 by roinachum
3
'Goto definition' doesn't work if there is a package import in the module header
#189 opened Dec 7, 2022 by lvoudour
1
Nested parenthesis within a port instantiation breaks syntax highlighting pattern on the next line
#188 opened Oct 26, 2022 by birdybro
4
Limit parsing when file count is greater than threshold
#186 opened Oct 9, 2022 by joecrop
Compile action doesn't work if file isn't within workspace
#176 opened Sep 6, 2022 by agg23
Pure virtual method declarations aren't parsed properly
#175 opened Aug 30, 2022 by tudortimi
1
Interface classes aren't parsed properly
#174 opened Aug 27, 2022 by tudortimi
Brackets in language configuration
#169 opened Jun 29, 2022 by hankhsu1996
1
Extension causes JS heap allocation failure
#166 opened May 25, 2022 by emroch
2
extension required many CPU used in TOP
#165 opened May 23, 2022 by huanghx1990
3
Auto module instantiation cannot handle module with parameters correctly
#159 opened Apr 27, 2022 by yiancar
7
Found a bug.
#154 opened Apr 6, 2022 by guojiazhuxi
1
ifdef/else/`endif folding
#142 opened Feb 23, 2022 by eng-tp
3
Allow selecting your syntax highlighting if 2 extension offer syntax highlighting for SystemVerilog
#137 opened Dec 2, 2021 by mrvkino
3
`include directive should be allowed anywhere
#128 opened Aug 23, 2021 by DanChianucci
8
Syntax highlighting errors
#125 opened Jun 22, 2021 by sconwayaus
1
2
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