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Verilator problem matcher regex doesn't actually detect anything #231
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@alex-the-new-guy will you please test the update I made? |
So, I've been doing a bit of a refactoring of the parser pipeline. Veeery slowly bc busy with work and university. I hope to finish it over the weekend and I can incorporate the changes you've made if you give me link to repo. |
@alex-the-new-guy the proper merge procedure is:
I'll leave my changes in master for now, and you can modify them as part of your pull request. I only changed one file: https://github.com/eirikpre/VSCode-SystemVerilog/pull/237/files#diff-7ae45ad102eab3b6d7e7896acd08c427a9b25b346470d7bc6507b6481575d519 |
Windows 11, using latest version of Verilator and extension, both build from git today.
Test modules are:
top.v
submodule.v
Verilator output is:
Which leads to no problems being detected.
From what I've deduced from using a regex debugger, the issue comes from file line being included with column name and general mismatch between match groups in regex and sections
Adding regex to match Verilog and SystemVerilog file extensions and fixing group indexes so that problem matcher objects are as listed below, seems to fix the issue.
package.json
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