- 🔭 I’m currently working on ASIC_VLSI
- 👨🏼🔬 I’m currently learning C/Python
- 👯 I’m looking to collaborate on ASIC_VLSI_Projects
- 🤔 Ask me about ASIC_VLSI
🎓
Studying
Bachelor of Technology in Electronics and communication from GLA University Mathura. Skilled in Communication, Teamwork, VLSI Design, Cadence
-
GLA University
- Mathura
- [email protected]
- in/ekansh-bansal-04ek122002
- @EkanshBansal5
Pinned Loading
-
100DaysofRTL
100DaysofRTL Public"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.