Name		Name	Last commit message	Last commit date
Latest commit History 11 Commits
sev_segment		sev_segment
uart_rx_tx		uart_rx_tx
verilog_files		verilog_files
README.md		README.md
counter_clk_div.v		counter_clk_div.v
counter_led_works.v		counter_led_works.v
dff.v		dff.v
full_adder_structural.v		full_adder_structural.v
init.dat		init.dat
q1_memory_bl_ram_vio_ila.v		q1_memory_bl_ram_vio_ila.v
structural_mux2.v		structural_mux2.v
test_counter.v		test_counter.v
uart_rx_send_test.py		uart_rx_send_test.py
uart_rx_sweep_test.py		uart_rx_sweep_test.py
uart_tx.py		uart_tx.py