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Read xtal freq directly from PCR #1005

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Merged
bugadani merged 1 commit into from
Feb 11, 2026
+10 −6
Merged

Read xtal freq directly from PCR #1005

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3 changes: 2 additions & 1 deletion .gitignore
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Original file line number Diff line number Diff line change
Expand Up @@ -14,8 +14,9 @@ target/

# Ignore any files used by text editors or operating systems.
.vscode/
.zed/
.DS_Store
*.swp
.idea/

!espflash/src/target
!espflash/src/target
1 change: 1 addition & 0 deletions CHANGELOG.md
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Expand Up @@ -20,6 +20,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
### Fixed

- Fix Windows connection issue by aligning reset sequence with `esptool` including RTS/DTR workaround (#999)
- Fix board-info misreporting the crystal frequency of ESP32-C5 (#1005)

### Removed

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12 changes: 7 additions & 5 deletions espflash/src/target/mod.rs
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Expand Up @@ -911,12 +911,14 @@ impl Chip {
}
Chip::Esp32c3 => Ok(XtalFrequency::_40Mhz), // Fixed frequency
Chip::Esp32c5 => {
const UART_CLKDIV_REG: u32 = 0x6000_0014; // UART0_BASE_REG + 0x14
const UART_CLKDIV_MASK: u32 = 0xfffff;
const XTAL_CLK_DIVIDER: u32 = 1;
const PCR_SYSCLK_CONF_REG: u32 = 0x6009_6110; // PCR_BASE_REG + 0x110
const PCR_CLK_XTAL_FREQ_MASK: u32 = 0x7F;
const PCR_CLK_XTAL_FREQ_SHIFT: u32 = 24;
Comment on lines +914 to +916
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@SergioGasquez SergioGasquez Feb 11, 2026

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Source for reference: https://github.com/espressif/esptool/blob/deca775e38ce5f096b6e94a8bd5db74c6fc44c45/esptool/targets/esp32c5.py#L59-L61

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@bugadani bugadani Feb 11, 2026

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Actually I just read this out of the TRM, but sure we can say it comes from esptool :D


let sysclk_conf_reg = connection.read_reg(PCR_SYSCLK_CONF_REG)?;
let est_xtal =
(sysclk_conf_reg >> PCR_CLK_XTAL_FREQ_SHIFT) & PCR_CLK_XTAL_FREQ_MASK;

let uart_div = connection.read_reg(UART_CLKDIV_REG)? & UART_CLKDIV_MASK;
let est_xtal = (connection.baud()? * uart_div) / 1_000_000 / XTAL_CLK_DIVIDER;
let norm_xtal = if est_xtal > 45 {
XtalFrequency::_48Mhz
} else {
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