Discard IndOffXX style and let legitimize_address() fix any out-of-ra…

…nge immediate offsets

src/hotspot/cpu/aarch64/aarch64_vector.ad

@@ -345,7 +345,7 @@ source %{
 // ------------------------------ Vector load/store ----------------------------
 
 // Load Vector (16 bits)
-instruct loadV2(vReg dst, vmem2 mem) %{
+instruct loadV2(vReg dst, vmem mem) %{
   predicate(n->as_LoadVector()->memory_size() == 2);
   match(Set dst (LoadVector mem));
   format %{ "loadV2 $dst, $mem\t# vector (16 bits)" %}
@@ -354,7 +354,7 @@ instruct loadV2(vReg dst, vmem2 mem) %{
 %}
 
 // Store Vector (16 bits)
-instruct storeV2(vReg src, vmem2 mem) %{
+instruct storeV2(vReg src, vmem mem) %{
   predicate(n->as_StoreVector()->memory_size() == 2);
   match(Set mem (StoreVector mem src));
   format %{ "storeV2 $mem, $src\t# vector (16 bits)" %}
@@ -363,7 +363,7 @@ instruct storeV2(vReg src, vmem2 mem) %{
 %}
 
 // Load Vector (32 bits)
-instruct loadV4(vReg dst, vmem4 mem) %{
+instruct loadV4(vReg dst, vmem mem) %{
   predicate(n->as_LoadVector()->memory_size() == 4);
   match(Set dst (LoadVector mem));
   format %{ "loadV4 $dst, $mem\t# vector (32 bits)" %}
@@ -372,7 +372,7 @@ instruct loadV4(vReg dst, vmem4 mem) %{
 %}
 
 // Store Vector (32 bits)
-instruct storeV4(vReg src, vmem4 mem) %{
+instruct storeV4(vReg src, vmem mem) %{
   predicate(n->as_StoreVector()->memory_size() == 4);
   match(Set mem (StoreVector mem src));
   format %{ "storeV4 $mem, $src\t# vector (32 bits)" %}
@@ -381,7 +381,7 @@ instruct storeV4(vReg src, vmem4 mem) %{
 %}
 
 // Load Vector (64 bits)
-instruct loadV8(vReg dst, vmem8 mem) %{
+instruct loadV8(vReg dst, vmem mem) %{
   predicate(n->as_LoadVector()->memory_size() == 8);
   match(Set dst (LoadVector mem));
   format %{ "loadV8 $dst, $mem\t# vector (64 bits)" %}
@@ -390,7 +390,7 @@ instruct loadV8(vReg dst, vmem8 mem) %{
 %}
 
 // Store Vector (64 bits)
-instruct storeV8(vReg src, vmem8 mem) %{
+instruct storeV8(vReg src, vmem mem) %{
   predicate(n->as_StoreVector()->memory_size() == 8);
   match(Set mem (StoreVector mem src));
   format %{ "storeV8 $mem, $src\t# vector (64 bits)" %}
@@ -399,7 +399,7 @@ instruct storeV8(vReg src, vmem8 mem) %{
 %}
 
 // Load Vector (128 bits)
-instruct loadV16(vReg dst, vmem16 mem) %{
+instruct loadV16(vReg dst, vmem mem) %{
   predicate(n->as_LoadVector()->memory_size() == 16);
   match(Set dst (LoadVector mem));
   format %{ "loadV16 $dst, $mem\t# vector (128 bits)" %}
@@ -408,7 +408,7 @@ instruct loadV16(vReg dst, vmem16 mem) %{
 %}
 
 // Store Vector (128 bits)
-instruct storeV16(vReg src, vmem16 mem) %{
+instruct storeV16(vReg src, vmem mem) %{
   predicate(n->as_StoreVector()->memory_size() == 16);
   match(Set mem (StoreVector mem src));
   format %{ "storeV16 $mem, $src\t# vector (128 bits)" %}

src/hotspot/cpu/aarch64/aarch64_vector_ad.m4

@@ -338,7 +338,7 @@ dnl VECTOR_LOAD_STORE($1,   $2,     $3,       $4,    $5  )
 dnl VECTOR_LOAD_STORE(type, nbytes, arg_name, nbits, size)
 define(`VECTOR_LOAD_STORE', `
 // ifelse(load, $1, Load, Store) Vector ($4 bits)
-instruct $1V$2(vReg $3, vmem$2 mem) %{
+instruct $1V$2(vReg $3, vmem mem) %{
   predicate(`n->as_'ifelse(load, $1, Load, Store)Vector()->memory_size() == $2);
   match(Set ifelse(load, $1, dst (LoadVector mem), mem (StoreVector mem src)));
   format %{ "$1V$2 ifelse(load, $1, `$dst, $mem', `$mem, $src')\t# vector ($4 bits)" %}

src/hotspot/cpu/aarch64/ad_encode.m4

@@ -34,7 +34,7 @@ define(access, `
 define(load,`
   // This encoding class is generated automatically from ad_encode.m4.
   // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
-  enc_class aarch64_enc_$2($1 dst, memory$5 mem) %{dnl
+  enc_class aarch64_enc_$2($1 dst, memory mem) %{dnl
 access(dst,$2,$3,$4,$5)')dnl
 load(iRegI,ldrsbw,,,1)
 load(iRegI,ldrsb,,,1)
@@ -53,12 +53,12 @@ load(vRegD,ldrd,Float,,8)
 define(STORE,`
   // This encoding class is generated automatically from ad_encode.m4.
   // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
-  enc_class aarch64_enc_$2($1 src, memory$5 mem) %{dnl
+  enc_class aarch64_enc_$2($1 src, memory mem) %{dnl
 access(src,$2,$3,$4,$5)')dnl
 define(STORE0,`
   // This encoding class is generated automatically from ad_encode.m4.
   // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
-  enc_class aarch64_enc_$2`'0(memory$4 mem) %{
+  enc_class aarch64_enc_$2`'0(memory mem) %{
     choose(masm,zr,$2,$mem->opcode(),
         as_$3Register($mem$$base),$mem$$index,$mem$$scale,$mem$$disp,$4)')dnl
 STORE(iRegI,strb,,,1)
@@ -82,7 +82,7 @@ STORE(vRegD,strd,Float,,8)
 
   // This encoding class is generated automatically from ad_encode.m4.
   // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
-  enc_class aarch64_enc_strb0_ordered(memory4 mem) %{
+  enc_class aarch64_enc_strb0_ordered(memory mem) %{
       __ membar(Assembler::StoreStore);
       loadStore(masm, &MacroAssembler::strb, zr, $mem->opcode(),
                as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 1);

src/hotspot/cpu/aarch64/gc/x/x_aarch64.ad

@@ -1,5 +1,5 @@
 //
-// Copyright (c) 2019, 2023, Oracle and/or its affiliates. All rights reserved.
+// Copyright (c) 2019, 2024, Oracle and/or its affiliates. All rights reserved.
 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 //
 // This code is free software; you can redistribute it and/or modify it
@@ -51,7 +51,7 @@ static void x_load_barrier_slow_path(MacroAssembler* masm, const MachNode* node,
 %}
 
 // Load Pointer
-instruct xLoadP(iRegPNoSp dst, memory8 mem, rFlagsReg cr)
+instruct xLoadP(iRegPNoSp dst, memory mem, rFlagsReg cr)
 %{
   match(Set dst (LoadP mem));
   predicate(UseZGC && !ZGenerational && !needs_acquiring_load(n) && (n->as_Load()->barrier_data() != 0));
@@ -62,7 +62,13 @@ instruct xLoadP(iRegPNoSp dst, memory8 mem, rFlagsReg cr)
   format %{ "ldr  $dst, $mem" %}
 
   ins_encode %{
-    const Address ref_addr = mem2address($mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
+    Address ref_addr = mem2address($mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
+    if (ref_addr.getMode() == Address::base_plus_offset) {
+      // Fix up any out-of-range offsets.
+      assert_different_registers(rscratch1, as_Register($mem$$base));
+      assert_different_registers(rscratch1, $dst$$Register);
+      ref_addr = __ legitimize_address(ref_addr, 8, rscratch1);
+    }
     __ ldr($dst$$Register, ref_addr);
     x_load_barrier(masm, this, ref_addr, $dst$$Register, rscratch2 /* tmp */, barrier_data());
   %}

src/hotspot/cpu/aarch64/gc/z/z_aarch64.ad

@@ -1,5 +1,5 @@
 //
-// Copyright (c) 2019, 2023, Oracle and/or its affiliates. All rights reserved.
+// Copyright (c) 2019, 2024, Oracle and/or its affiliates. All rights reserved.
 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 //
 // This code is free software; you can redistribute it and/or modify it
@@ -100,7 +100,7 @@ static void z_store_barrier(MacroAssembler* masm, const MachNode* node, Address
 %}
 
 // Load Pointer
-instruct zLoadP(iRegPNoSp dst, memory8 mem, rFlagsReg cr)
+instruct zLoadP(iRegPNoSp dst, memory mem, rFlagsReg cr)
 %{
   match(Set dst (LoadP mem));
   predicate(UseZGC && ZGenerational && !needs_acquiring_load(n) && n->as_Load()->barrier_data() != 0);
@@ -111,7 +111,13 @@ instruct zLoadP(iRegPNoSp dst, memory8 mem, rFlagsReg cr)
   format %{ "ldr  $dst, $mem" %}
 
   ins_encode %{
-    const Address ref_addr = mem2address($mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
+    Address ref_addr = mem2address($mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
+    if (ref_addr.getMode() == Address::base_plus_offset) {
+      // Fix up any out-of-range offsets.
+      assert_different_registers(rscratch2, as_Register($mem$$base));
+      assert_different_registers(rscratch2, $dst$$Register);
+      ref_addr = __ legitimize_address(ref_addr, 8, rscratch2);
+    }
     __ ldr($dst$$Register, ref_addr);
     z_load_barrier(masm, this, ref_addr, $dst$$Register, rscratch1);
   %}

src/hotspot/share/adlc/archDesc.cpp

@@ -249,15 +249,6 @@ void ArchDesc::inspectOperands() {
     MatchRule *mrule = op->_matrule;
     Predicate *pred  = op->_predicate;
 
-    // If there are multiple arguments, we need to insert
-    // parentheses for predicate so that these arguments
-    // can be chained together logically with "&&".
-    if (op->_matrule &&
-        !(op->_matrule->_lChild == nullptr &&
-          op->_matrule->_rChild == nullptr)) {
-      pred = InstructForm::build_predicate(op->_matrule, op->_predicate);
-    }
-
     // Grab the machine type of the operand
     const char  *rootOp    = op->_ident;
     mrule->_machType  = rootOp;
@@ -305,7 +296,7 @@ void ArchDesc::inspectInstructions() {
     if ( instr->_matrule == nullptr )  continue;
 
     MatchRule &mrule = *instr->_matrule;
-    Predicate* pred  = InstructForm::build_predicate(instr->_matrule, instr->_predicate);
+    Predicate *pred  =  instr->build_predicate();
 
     // Grab the machine type of the operand
     const char  *rootOp    = instr->_ident;

src/hotspot/share/adlc/formssel.cpp

@@ -1525,25 +1525,24 @@ void MachNodeForm::output(FILE *fp) {
 }
 
 //------------------------------build_predicate--------------------------------
-// Build predicates for instructions or operands.
-//
-// If the user uses the same operand name twice, we need to check that
-// the operands are pointer-equivalent in the DFA during the labeling process.
-Predicate* InstructForm::build_predicate(MatchRule* matrule, Predicate* predicate) {
+// Build instruction predicates.  If the user uses the same operand name
+// twice, we need to check that the operands are pointer-eequivalent in
+// the DFA during the labeling process.
+Predicate *InstructForm::build_predicate() {
   const int buflen = 1024;
   char buf[buflen], *s=buf;
   Dict names(cmpstr,hashstr,Form::arena);       // Map Names to counts
 
-  MatchNode* mnode =
-    strcmp(matrule->_opType, "Set") ? matrule : matrule->_rChild;
+  MatchNode *mnode =
+    strcmp(_matrule->_opType, "Set") ? _matrule : _matrule->_rChild;
   if (mnode != nullptr) mnode->count_instr_names(names);
 
   uint first = 1;
   // Start with the predicate supplied in the .ad file.
-  if (predicate) {
+  if (_predicate) {
     if (first) first = 0;
     strcpy(s, "("); s += strlen(s);
-    strncpy(s, predicate->_pred, buflen - strlen(s) - 1);
+    strncpy(s, _predicate->_pred, buflen - strlen(s) - 1);
     s += strlen(s);
     strcpy(s, ")"); s += strlen(s);
   }

src/hotspot/share/adlc/formssel.hpp

@@ -221,11 +221,10 @@ class InstructForm : public Form {
   // Does this instruction need a base-oop edge?
   int needs_base_oop_edge(FormDict &globals) const;
 
-  // Build predicates for instructions or operands.
-  //
-  // If the user uses the same operand name twice, we need to check that the
-  // operands are pointer-equivalent in the DFA during the labeling process.
-  static Predicate* build_predicate(MatchRule* matrule, Predicate* predicate);
+  // Build instruction predicates.  If the user uses the same operand name
+  // twice, we need to check that the operands are pointer-eequivalent in
+  // the DFA during the labeling process.
+  Predicate *build_predicate();
 
   virtual void        build_components(); // top-level operands
   // Return zero-based position in component list; -1 if not in list.

src/hotspot/share/adlc/output_c.cpp

@@ -4316,7 +4316,7 @@ void ArchDesc::identify_cisc_spill_instructions() {
       if ( instr->_matrule == nullptr )  continue;
 
       MatchRule &mrule = *instr->_matrule;
-      Predicate* pred  = InstructForm::build_predicate(instr->_matrule, instr->_predicate);
+      Predicate *pred  =  instr->build_predicate();
 
       // Grab the machine type of the operand
       const char *rootOp = instr->_ident;
@@ -4337,7 +4337,7 @@ void ArchDesc::identify_cisc_spill_instructions() {
             && (instr2->reduce_result() != nullptr) // want same result
             && (strcmp(result, instr2->reduce_result()) == 0)) {
           MatchRule &mrule2 = *instr2->_matrule;
-          Predicate* pred2  = InstructForm::build_predicate(instr2->_matrule, instr2->_predicate);
+          Predicate *pred2  =  instr2->build_predicate();
           found_cisc_alternate = instr->cisc_spills_to(*this, instr2);
         }
       }