Upstream ARC-V RHX-100#176

Draft

MichielDerhaeg wants to merge 17 commits intomichiel/upstream_rmx100from

michiel/upstream_rhx100

Commits on Nov 6, 2025

arcv: Add initial scheduling scheme.

claziss
authored and
MichielDerhaeg
committed
arcv: fuse load-immediate with store

artemiy-volkov
authored and
MichielDerhaeg
committed
arcv: Introduce riscv_is_micro_arch ()

Shahab Vahedi
authored and
MichielDerhaeg
committed
arcv: fuse load-immediate with dependent branch

artemiy-volkov
authored and
MichielDerhaeg
committed
arcv: implement TARGET_SCHED_FUSION_PRIORITY

artemiy-volkov
authored and
MichielDerhaeg
committed
arcv: fuse load/store + register post-{inc,dec}rement

artemiy-volkov
authored and
MichielDerhaeg
committed
arcv: fuse load/store with lui

artemiy-volkov
authored and
MichielDerhaeg
committed
arcv: create a 32-bit integer multiply-add instruction pattern

artemiy-volkov
authored and
MichielDerhaeg
committed
arcv: fuse integer multiply-add instruction pairs

artemiy-volkov
authored and
MichielDerhaeg
committed
arcv: implement bit-extract fusion

artemiy-volkov
authored and
MichielDerhaeg
committed
arcv: allow inverted instruction order for some fusion types

artemiy-volkov
authored and
MichielDerhaeg
committed
arcv: add scheduling implementation for RHX-100

artemiy-volkov
authored and
MichielDerhaeg
committed
arcv: adjust scheduling priority of memop pairs for RHX-100

artemiy-volkov
authored and
MichielDerhaeg
committed
arcv: fuse LH+LH and LB+LB instruction pairs

artemiy-volkov
authored and
MichielDerhaeg
committed
arcv: do not emit 64-bit MAC pairs for 32-bit data

artemiy-volkov
authored and
MichielDerhaeg
committed
arcv: Disable *<any_extract...>3 when fusion is available
MichielDerhaeg
committed
fixup! arcv: Add initial scheduling scheme.
MichielDerhaeg
committed

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Upstream ARC-V RHX-100#176

Upstream ARC-V RHX-100#176
MichielDerhaeg wants to merge 17 commits intomichiel/upstream_rmx100from
michiel/upstream_rhx100

Commits on Nov 6, 2025

arcv: Add initial scheduling scheme.

arcv: fuse load-immediate with store

arcv: Introduce riscv_is_micro_arch ()

arcv: fuse load-immediate with dependent branch

arcv: implement TARGET_SCHED_FUSION_PRIORITY

arcv: fuse load/store + register post-{inc,dec}rement

arcv: fuse load/store with lui

arcv: create a 32-bit integer multiply-add instruction pattern

arcv: fuse integer multiply-add instruction pairs

arcv: implement bit-extract fusion

arcv: allow inverted instruction order for some fusion types

arcv: add scheduling implementation for RHX-100

arcv: adjust scheduling priority of memop pairs for RHX-100

arcv: fuse LH+LH and LB+LB instruction pairs

arcv: do not emit 64-bit MAC pairs for 32-bit data

arcv: Disable *<any_extract...>3 when fusion is available

fixup! arcv: Add initial scheduling scheme.

Upstream ARC-V RHX-100#176MichielDerhaeg wants to merge 17 commits intomichiel/upstream_rmx100foss-for-synopsys-dwc-arc-processors/gcc:michiel/upstream_rmx100from michiel/upstream_rhx100foss-for-synopsys-dwc-arc-processors/gcc:michiel/upstream_rhx100Copy head branch name to clipboard

Commits

Commits on Nov 6, 2025

Upstream ARC-V RHX-100#176
MichielDerhaeg wants to merge 17 commits intomichiel/upstream_rmx100from
michiel/upstream_rhx100