Add basic DE0 Support (~3MH/s)

boards/DE0/DE0.qsf

@@ -0,0 +1,18 @@
+set_global_assignment -name DEVICE EP3C16F484C6
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY quartus_output
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 65%
+
+
+# Clocks
+set_location_assignment PIN_G21 -to MAIN_CLK
+

boards/DE0/DE0.sdc

@@ -0,0 +1,27 @@
+##
+#
+# Copyright (c) 2011-2012 [email protected]
+#
+#
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+# 
+##
+
+create_clock -period 20.000 -name MAIN_CLK MAIN_CLK
+
+derive_pll_clocks
+derive_clock_uncertainty
+
+

projects/DE0/fpgaminer.qpf

@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2010 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
+# Date created = 19:43:05  May 18, 2011
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "10.0"
+DATE = "19:43:05  May 18, 2011"
+
+# Revisions
+
+PROJECT_REVISION = "fpgaminer"
+

projects/DE0/fpgaminer.qsf

@@ -0,0 +1,34 @@
+source "../../boards/DE0/DE0.qsf"
+
+set_global_assignment -name TOP_LEVEL_ENTITY fpgaminer_top
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "10.0 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:52:09  MAY 05, 2011"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON
+
+
+set_global_assignment -name VERILOG_MACRO "CONFIG_LOOP_LOG2=4"
+set_global_assignment -name VERILOG_MACRO "MAIN_CLK_FREQUENCY=50"
+set_global_assignment -name VERILOG_MACRO "MAIN_CLK_DIVIDE=1"
+set_global_assignment -name VERILOG_MACRO "MAIN_CLK_MULTIPLY=1"
+
+
+set_global_assignment -name SDC_FILE ../../boards/DE0/DE0.sdc
+set_global_assignment -name VERILOG_FILE ../../cores/unoptimized/sha256_transform.v
+set_global_assignment -name VERILOG_FILE "../../cores/unoptimized/sha-256-functions.v"
+set_global_assignment -name VERILOG_FILE ../../cores/unoptimized_virtual_wire_top.v
+set_global_assignment -name VERILOG_FILE ../../cores/cyclone_iv_pll/hashing_pll.v
+set_global_assignment -name VERILOG_FILE ../../cores/virtual_wire/virtual_wire.v
+
+
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top