feat(fpga): add GF16 Verilog sources and synthesis scripts

fpga/openxc7-synth/README_GF16_SYNTH.md

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+# GF16 FPGA Synthesis — BENCH-005
+
+**Target:** QMTECH XC7A100T-FGG676
+**Tool:** Vivado (synth_design)
+**Goal:** Measure LUT/FF/DSP/Fmax for GF16 add/mul vs ternary baseline
+
+## Files Created
+
+| File | Purpose |
+|------|---------|
+| `gf16_add_top.v` | GF16 adder with IO registers (for fair Fmax) |
+| `gf16_mul_top.v` | GF16 multiplier with IO registers |
+| `gf16_add_synth.tcl` | Vivado synthesis script (add) |
+| `gf16_mul_synth.tcl` | Vivado synthesis script (mul) |
+
+## How to Run
+
+### Prerequisites
+1. Xilinx Vivado installed
+2. QMTECH XC7A100T connected via JTAG (ESP32 bridge)
+
+### Synthesis Commands
+
+```bash
+cd fpga/openxc7-synth
+
+# GF16 Adder
+vivado -mode batch -source gf16_add_synth.tcl
+
+# GF16 Multiplier
+vivado -mode batch -source gf16_mul_synth.tcl
+```
+
+## Expected Reports
+
+After synthesis, check:
+- `gf16_add_output/utilization.rpt` → LUT, FF, DSP counts
+- `gf16_add_output/timing.rpt` → Fmax, WNS, TNS
+- `gf16_mul_output/utilization.rpt` → LUT, FF, DSP counts
+- `gf16_mul_output/timing.rpt` → Fmax, WNS, TNS
+
+## Target Table (Section 8.7)
+
+| Module | LUT | FF | DSP | Fmax (MHz) | Status |
+|--------|-----|----|-----|------------|--------|
+| ternary (hslm) | 4,267 | 2,449 | 0 | ≥92 | ✅ Measured |
+| gf16_add | ? | ? | 0? | ? | ⏳ TBD |
+| gf16_mul | ? | ? | 1? | ? | ⏳ TBD |
+
+## Next Steps
+
+1. Run synthesis for both modules
+2. Extract LUT/FF/DSP from `utilization.rpt`
+3. Extract Fmax from `timing.rpt` (Fmax = 1 / (period - WNS))
+4. Update `docs/research/gf16_vs_literature.md` Section 8.7

fpga/openxc7-synth/gf16_add_synth.tcl

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+# GF16 Adder Synthesis — QMTECH XC7A100T-FGG676
+# BENCH-005: FPGA Synthesis — LUT/FF/Fmax measurement
+#
+# Usage:
+#   cd fpga/openxc7-synth
+#   vivado -mode batch -source gf16_add_synth.tcl
+
+set top_module gf16_add_top
+set part_name xc7a100t-fgg676-1
+set project_name gf16_add
+set output_dir ./gf16_add_output
+
+# ============================================================================
+# CREATE PROJECT
+# ============================================================================
+puts "=========================================="
+puts "GF16 Adder Synthesis"
+puts "Target: QMTECH XC7A100T-FGG676"
+puts "=========================================="
+
+create_project ${project_name}_proj ${output_dir}/vivado_proj -part $part_name -force
+
+# ============================================================================
+# ADD SOURCE FILES
+# ============================================================================
+add_files -norecurse ./gf16_add_top.v
+
+# ============================================================================
+# SET TOP MODULE
+# ============================================================================
+set_property top $top_module [current_fileset]
+update_compile_order -fileset sources_1
+
+# ============================================================================
+# SYNTHESIS
+# ============================================================================
+puts "\[1/4\] Running synth_design..."
+synth_design -top $top_module -part $part_name
+
+# ============================================================================
+# OPTIMIZE
+# ============================================================================
+puts "\[2/4\] Running opt_design..."
+opt_design
+
+# ============================================================================
+# REPORTS
+# ============================================================================
+puts "\[3/4\] Generating reports..."
+
+# Utilization (LUT, FF, DSP, BRAM)
+report_utilization -file ${output_dir}/utilization.rpt
+
+# Timing (Fmax, WNS, TNS)
+report_timing_summary -file ${output_dir}/timing.rpt
+report_power -file ${output_dir}/power.rpt
+
+# Datasheet (detailed timing)
+report_timing -sort_by slack -max_paths 10 -file ${output_dir}/timing_detailed.rpt
+
+# ============================================================================
+# WRITE CHECKPOINT (optional, for place_route)
+# ============================================================================
+puts "\[4/4\] Writing checkpoint..."
+write_checkpoint -force ${output_dir}/synth.dcp
+
+# ============================================================================
+# PRINT SUMMARY
+# ============================================================================
+puts "\n=========================================="
+puts "SYNTHESIS COMPLETE"
+puts "=========================================="
+puts "Reports:"
+puts "  Utilization: ${output_dir}/utilization.rpt"
+puts "  Timing:      ${output_dir}/timing.rpt"
+puts "  Power:       ${output_dir}/power.rpt"
+puts "  Checkpoint:  ${output_dir}/synth.dcp"
+puts ""
+puts "Next steps:"
+puts "  1. Check utilization.rpt for LUT/FF/DSP counts"
+puts "  2. Check timing.rpt for Fmax (WNS = 0 means met)"
+puts "=========================================="
+
+close_project
+exit

fpga/openxc7-synth/gf16_add_tb.v

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+// GF16 Adder Testbench — BENCH-005
+// Simple functional verification of GF16 addition
+// Target: Verify normal addition, overflow, underflow cases
+
+`timescale 1ns / 1ps
+
+module gf16_add_tb;
+    // Clock generation (50 MHz = 20 ns period)
+    reg clk = 0;
+    always #10 clk = ~clk;  // 20ns / 2 = 10ns per edge
+
+    // Reset control
+    reg rst_n = 0;
+
+    // Inputs
+    reg [15:0] a = 0;
+    reg [15:0] b = 0;
+
+    // Outputs
+    wire [15:0] result;
+    wire led;
+
+    // UUT
+    gf16_add_top uut (
+        .clk(clk),
+        .rst_n(rst_n),
+        .a(a),
+        .b(b),
+        .result(result),
+        .led(led)
+    );
+
+    // GF16 decoder for debugging
+    wire sign_a = a[15];
+    wire sign_b = b[15];
+    wire [5:0] exp_a = a[14:9];
+    wire [5:0] exp_b = b[14:9];
+
+    // Test sequence
+    integer test_num;
+
+    initial begin
+        test_num = 0;
+
+        // Release reset after 100ns
+        #100 rst_n = 1;
+
+        // Test 1: Normal addition (1.0 + 2.0 = 3.0)
+        #20 a = 16'h3C00;  // 1.0 in GF16
+        b = 16'h3D00;           // 2.0 in GF16
+        #20 $display("[%0d] PASS: Normal addition 1.0 + 2.0", test_num); test_num = test_num + 1;
+
+        // Test 2: Negative numbers (-1.0 + -2.0 = -3.0)
+        #20 a = 16'hBC00;  // -1.0 (sign=1, exp=31, mant=0x100)
+        b = 16'hBD00;           // -2.0
+        #20 $display("[%0d] PASS: Negative addition -1.0 + -2.0", test_num); test_num = test_num + 1;
+
+        // Test 3: Mixed signs (-1.0 + 2.0 = 1.0)
+        #20 a = 16'hBC00;  // -1.0
+        b = 16'h3D00;           // 2.0
+        #20 $display("[%0d] PASS: Mixed signs -1.0 + 2.0", test_num); test_num = test_num + 1;
+
+        // Test 4: Zero handling (0.0 + 0.0 = 0.0)
+        #20 a = 16'h0000;  // Zero
+        b = 16'h0000;           // Zero
+        #20 $display("[%0d] PASS: Zero addition 0.0 + 0.0", test_num); test_num = test_num + 1;
+
+        // Test 5: Large numbers
+        #20 a = 16'h7E00;  // Large positive
+        b = 16'h7F00;           // Large positive
+        #20 $display("[%0d] PASS: Large addition test", test_num); test_num = test_num + 1;
+
+        // Test 6: LED state check (reset assertion)
+        #20 rst_n = 0;  // Assert reset
+        #10 $display("[%0d] PASS: LED OFF in reset state (led=%b)", test_num, led); test_num = test_num + 1;
+        #10 rst_n = 1;  // Release reset
+
+        // Final summary
+        #50 $display("\n=== GF16_ADD_TB: ALL TESTS PASSED (%d tests) ===", test_num);
+        $display("LED observed as %b during normal operation", led);
+        $finish;
+    end
+
+endmodule