[WIP] Implement a VHDL backend #122
Commits on May 21, 2020
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Copy the verilog backend as vhdl_backend.cc
Now need to start the actual conversion of syntax
Commits on May 22, 2020
Commits on May 23, 2020
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Mark dump_attributes as PORTING REQUIRED again
More nontrivial design decisions need to be made before I actually write the code for this
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Implement dump_constant and remove decimal option
Completely removing decimal functionality may come back to bite me later...I'll see
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Commits on May 25, 2020
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Port dump_cell_expr_uniop and dump_cell_expr_binop
dump_cell_expr_binop may need adjustments because of STD_LOGIC_VECTOR vs UNSIGNED/SIGNED
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Replace $signed with signed in dump_cell_expr_port
I am not marking this as done until I better understand the context in which this function is called
Commits on May 28, 2020
Commits on May 30, 2020
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Port syntax gen of is_reg_wire
TODO: do reg/wire distinctions make sense for a VHDL backend?
Commits on May 31, 2020
Commits on Jun 3, 2020
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Initial pass of porting dump_cell_expr
Items labelled unported have not been changed yet, and everything else is subject to change
Commits on Jun 5, 2020
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Adjustments to autogenerated IDs to ensure numbered internal signals …
…are valid VHDL identifiers
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Initial port of module dumping
At this point the backend should produce valid VHDL for a subset of RTLIL netlists Finishing the port of dump_cell_expr and other functions will take time
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Port bit selection of cellname
Other changes may be needed relating to invalid VHDL identifier characters
Commits on Jun 6, 2020
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Write function to get a sensitivity set given SigSpecs
This should be used to create sensitivity lists whenever creating processes
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Address Xiretza's review comment
The Verilog backend assumes that port_ids>=1 when valid, however...
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Commits on Jun 8, 2020
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Testing in progress, as well as handling 'X' constants
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Fix $pmux dump to use onehot strings instead of aggregates
This is valid VHDL-93 as well (besides of the aggregates breaking GHDL)
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Commits on Jun 9, 2020
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TODOs in code below, especially with $lt and related
Commits on Jun 13, 2020
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For hex consts, push '0's and include width when needed
Old stuff copied from Verilog did not follow VHDL spec Unfortunately all-unknown constants like 5x"ZZ" are invalid...
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Commits on Jul 28, 2020
Commits on Aug 2, 2020
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Part 1 of porting new FF changes
See YosysHQ/yosys@8fd4351 Still need to write the actual new FF code generation
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Commits on Aug 5, 2020
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Make memory_array_types a regular (sorted) set
It will usually be too small to reap the benefits of an amortized hashing implementation of a map
Commits on Aug 9, 2020
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Dump $assert cells as regular VHDL assert
See comment on ghdl/ghdl#1427
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Commits on Aug 10, 2020
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Copy over new dumping code and port clocked FF portions of it
TODO: dump latches (besides of sensitivity list which was ported here)
Commits on Aug 11, 2020
Commits on Aug 14, 2020
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Port latch generation code as well
This still needs testing, especially since opt_dff does not do latch transforms (yet)
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Commits on Sep 7, 2020
Commits on Oct 9, 2020
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reduce_(and|or|bool|xn?or) should work perfectly fine now, but s?sh(l|r) is probably still broken
Commits on Oct 13, 2020
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Replace "unclocked assertions" warning with "unclocked directives"
This is more accurate, especially since $assert is normal assert now
Commits on Nov 2, 2020
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Rename dump_memory to dump_memory_types
Prepare to bring in new refactoring of memory dumping from Verilog backend
Commits on Dec 17, 2020
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Port over Mem helper changes from Verilog backend
FF sensitivity lists not ported; see code comment for explanation
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Commits on Dec 20, 2020
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Put parentheses around output of dump_cell_expr_port in case concaten…
…ation happens All uses of dump_cell_expr_port are on the RHS of an expression
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Propagate LHS concatenation mode to various cell_expr dumps
TODO: concatenation handling may be broken outside of VHDL-2008 mode; handle this later
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Fix mult18x18d component to match yosys verilog
(cherry picked from commit 6671d04)
Commits on Dec 21, 2020
Commits on Jan 1, 2021
Commits on Jan 25, 2021
Commits on Feb 11, 2021
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Slight adjustments to formal cell dumping
* In std08 mode, avoid an explicit `='1'` for non-PSL asserts * Update the log_experiment call to reflect the use of non-PSL asserts
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Mark dump_memory_types as porting complete
Actually dumping memories though is currently an unresolved thing
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Initial (believed working) port of $lut cell dumping
Qualified expression part will probably be moved into dump_sigspec