Exclude substrate ground connections for Simulation

Solves efabless/caravel#54
heavySea · May 5, 2021 · 56ec9e6 · 56ec9e6
1 parent d0e49b9
commit 56ec9e6
Showing 1 changed file with 5 additions and 2 deletions.
diff --git a/verilog/rtl/mgmt_protect_hv.v b/verilog/rtl/mgmt_protect_hv.v
@@ -45,8 +45,11 @@ module mgmt_protect_hv (
 `ifdef USE_POWER_PINS
     // This is to emulate the substrate shorting grounds together for LVS
     // purposes
-    assign vssa2 = vssa1;
-    assign vssa1 = vssd;
+    `ifndef SIM
+        assign vssa2 = vssa1;
+        assign vssa1 = vssd;
+    `endif
+
 `endif
 
     // Logic high in the VDDA (3.3V) domains