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Add N290 GNU and QEMU-RISCV News #173

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Jan 24, 2025
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Add N290 GNU and QEMU-RISCV News #173

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Add N290 GNU News
Liaoshihua Jan 21, 2025
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Add N290 QEMU-RISCV News
Liaoshihua Jan 21, 2025
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42 changes: 42 additions & 0 deletions weekly-2025/2025-01-22.md
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### GCC

- [PATCH v5 1/4] RISC-V: Add Zicfiss ISA extension.
https://gcc.gnu.org/pipermail/gcc-patches/2025-January/673757.html

- [GCC16 stage 1][RFC][PATCH 0/3]extend "counted_by" attribute to pointer fields of structures
https://gcc.gnu.org/pipermail/gcc-patches/2025-January/673837.html

- [PATCH v3 1/2] RISC-V: Allocate the initial register in the expand phase for the vl of XTheadVector
https://gcc.gnu.org/pipermail/gcc-patches/2025-January/673873.html

- [PATCH]AArch64: Drop ILP32 from default elf multilibs after deprecation
https://gcc.gnu.org/pipermail/gcc-patches/2025-January/673905.html

- [PATCH 00/18] s390: arch15: Prepare for a future architecture
https://gcc.gnu.org/pipermail/gcc-patches/2025-January/674054.html

### BINUTILS

- [PATCH] RISC-V: Add .bfloat16 directive
https://sourceware.org/pipermail/binutils/2025-January/138862.html

- [PATCH] alpha, ld: remove -taso option
https://sourceware.org/pipermail/binutils/2025-January/138818.html

### GDB

- [PATCH 0/3] Remove mapped_index_base and slightly clean up DWARF reader
https://sourceware.org/pipermail/gdb-patches/2025-January/214805.html

- [PATCH 0/3] Add displaced stepping support for AMD GPUs
https://sourceware.org/pipermail/gdb-patches/2025-January/214750.html

### GLIBC

- RISC-V round_away () handling of non canonical rounding modes
https://sourceware.org/pipermail/libc-alpha/2025-January/164025.html

- [PATCH v3] RISC-V: add multiarch RVV support for memcpy using FMV IFUNC
https://sourceware.org/pipermail/libc-alpha/2025-January/164085.html

### LLVM/Clang/LLDB/LLD

本节内容来自 [LLVM Weekly 第 572 期](http://llvmweekly.org/issue/572)，
[Alex Bradbury](https://www.linkedin.com/in/alex-bradbury/) 大哥持续稳定输出。

### QEMU (RISC-V)

- [PATCH v2 0/2] target/riscv: throw debug exception before page fault
https://lists.nongnu.org/archive/html/qemu-devel/2025-01/msg03634.html

- [PULL v2 00/50] riscv-to-apply queue
https://lists.nongnu.org/archive/html/qemu-devel/2025-01/msg03477.html

- [PULL 1/5] target/riscv: Add RISC-V CSR qtest support
https://lists.nongnu.org/archive/html/qemu-devel/2025-01/msg03299.html

### RISC-V in China

### RT-Thread 社区
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