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Merge remote-tracking branch 'ian/dev' into dev
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Change-Id: I34656758e673603e91ba7175345f705c394aaad4
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@hoglet67
hoglet67 committed Jan 31, 2021
2 parents 2e0612a + 40df32b commit 20ce5f0
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Showing 57 changed files with 884 additions and 375 deletions.
4 changes: 2 additions & 2 deletions src/capture_line_default_twelvebits_8bpp_16bpp.S
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Original file line number Diff line number Diff line change
Expand Up @@ -134,7 +134,7 @@ capture_line_default_ninebitslo_16bpp:
push {lr}
SETUP_VSYNC_DEBUG_16BPP_R11
SKIP_PSYNC_NO_OLD_CPLD
SETUP_NINE_BITS_MASK_R14
SETUP_NINELO_BITS_MASK_R14
loop_9lobpp:
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
CAPTURE_NINELO_BITS_16BPP_LO r11 // input in r8
Expand Down Expand Up @@ -175,7 +175,7 @@ capture_line_default_ninebitshi_16bpp:
push {lr}
SETUP_VSYNC_DEBUG_16BPP_R11
SKIP_PSYNC_NO_OLD_CPLD
SETUP_NINE_BITS_MASK_R14
SETUP_NINEHI_BITS_MASK_R14
loop_9hibpp:
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
CAPTURE_NINEHI_BITS_16BPP_LO r11 // input in r8
Expand Down
4 changes: 2 additions & 2 deletions src/capture_line_default_twelvebits_double_8bpp_16bpp.S
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Original file line number Diff line number Diff line change
Expand Up @@ -108,7 +108,7 @@ capture_line_default_ninebitslo_double_16bpp:
push {lr}
SETUP_VSYNC_DEBUG_16BPP_R11
SKIP_PSYNC_NO_OLD_CPLD
SETUP_NINE_BITS_MASK_R14
SETUP_NINELO_BITS_MASK_R14
loop_16lobpp:
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
CAPTURE_NINELO_BITS_DOUBLE_16BPP r11 r5 // input in r8
Expand Down Expand Up @@ -140,7 +140,7 @@ capture_line_default_ninebitshi_double_16bpp:
push {lr}
SETUP_VSYNC_DEBUG_16BPP_R11
SKIP_PSYNC_NO_OLD_CPLD
SETUP_NINE_BITS_MASK_R14
SETUP_NINEHI_BITS_MASK_R14
loop_16hibpp:
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
CAPTURE_NINEHI_BITS_DOUBLE_16BPP r11 r5 // input in r8
Expand Down
215 changes: 188 additions & 27 deletions src/capture_line_fast_simple_16bpp.S
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4 changes: 2 additions & 2 deletions src/capture_line_fast_twelvebits_8bpp_16bpp.S
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Original file line number Diff line number Diff line change
Expand Up @@ -135,7 +135,7 @@ capture_line_fast_ninebitslo_16bpp:
push {lr}
SETUP_VSYNC_DEBUG_16BPP_R11
SKIP_PSYNC_NO_OLD_CPLD_FAST
SETUP_NINE_BITS_MASK_R14
SETUP_NINELO_BITS_MASK_R14
loop_16lobpp:
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
CAPTURE_NINELO_BITS_16BPP_LO r11 // input in r8
Expand Down Expand Up @@ -175,7 +175,7 @@ capture_line_fast_ninebitshi_16bpp:
push {lr}
SETUP_VSYNC_DEBUG_16BPP_R11
SKIP_PSYNC_NO_OLD_CPLD_FAST
SETUP_NINE_BITS_MASK_R14
SETUP_NINEHI_BITS_MASK_R14
loop_16hibpp:
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
CAPTURE_NINEHI_BITS_16BPP_LO r11 // input in r8
Expand Down
21 changes: 18 additions & 3 deletions src/defs.h
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Original file line number Diff line number Diff line change
Expand Up @@ -122,6 +122,11 @@
#define GPCLR0 (PERIPHERAL_BASE + 0x200028)
#define GPLEV0 (PERIPHERAL_BASE + 0x200034)
#define GPEDS0 (PERIPHERAL_BASE + 0x200040)
#define GPREN0 (PERIPHERAL_BASE + 0x20004C)
#define GPFEN0 (PERIPHERAL_BASE + 0x200058)
#define GPAREN0 (PERIPHERAL_BASE + 0x20007C)
#define GPAFEN0 (PERIPHERAL_BASE + 0x200088)

#define FIQCTRL (PERIPHERAL_BASE + 0x00B20C)

#define INTPEND2 (PERIPHERAL_BASE + 0x00B208)
Expand Down Expand Up @@ -150,7 +155,8 @@
#define O_NTSCPHASE 76
#define O_BORDER 80
#define O_DELAY 84
#define O_CAPTURE_LINE 88
#define O_INTENSITY 88
#define O_CAPTURE_LINE 92

#else

Expand All @@ -177,6 +183,7 @@ typedef struct {
int ntscphase; // NTSC artifact colour phase
int border; // border logical colour
int delay; // delay value from sampling menu & 3
int intensity; // scanline intensity
int (*capture_line)(); // the capture line function to use
int px_sampling; // whether to sample normally, sub-sample or pixel double

Expand Down Expand Up @@ -228,7 +235,7 @@ typedef struct {
#define VERSION_MASK (1U << VERSION_PIN)
#define STROBE_MASK (1U << STROBE_PIN)
#define SP_DATA_MASK (1U << SP_DATA_PIN)

#define MUX_MASK (1U << MUX_PIN)

#define GPIO_FLOAT 0x00
#define GPIO_PULLDOWN 0x01
Expand Down Expand Up @@ -280,7 +287,7 @@ typedef struct {
#define OTHER_HSYNC_THRESHOLD 9000
#define EQUALISING_THRESHOLD 3400 // equalising pulses are half sync pulse length and must be filtered out
#define FRAME_MINIMUM 10000000 // 10ms
#define FRAME_TIMEOUT 24000000 // 24ms which is over a frame / field @ 50Hz (20ms)
#define FRAME_TIMEOUT 30000000 // 30ms which is over a frame / field @ 50Hz (20ms)
#define LINE_MINIMUM 20000 // 20uS
#define HSYNC_SCROLL_LO (4000 - 224)
#define HSYNC_SCROLL_HI (4000 + 224)
Expand Down Expand Up @@ -401,4 +408,12 @@ typedef struct {
#define GP_CLK1_DIV (volatile uint32_t *)(PERIPHERAL_BASE + 0x10107C)
#define CM_PLLA (volatile uint32_t *)(PERIPHERAL_BASE + 0x101104)

#define CM_BASE (volatile uint32_t *)(PERIPHERAL_BASE + 0x101000)

#define SCALER_DISPLIST1 (volatile uint32_t *)(PERIPHERAL_BASE + 0x400024)
#define SCALER_DISPLAY_LIST (volatile uint32_t *)(PERIPHERAL_BASE + 0x402000)

#define PIXEL_FORMAT 1 // RGBA4444
#define PIXEL_ORDER 3 // ABGR

#endif
14 changes: 9 additions & 5 deletions src/filesystem.c
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Original file line number Diff line number Diff line change
Expand Up @@ -124,9 +124,15 @@ static int generate_png(capture_info_t *capinfo, uint8_t **png, unsigned int *pn
uint8_t single_pixel_lo = *fp++;
uint8_t single_pixel_hi = *fp++;
int single_pixel = single_pixel_lo | (single_pixel_hi << 8);
uint8_t single_pixel_R = single_pixel >> 12;
uint8_t single_pixel_G = (single_pixel >> 7) & 0x0f;
uint8_t single_pixel_B = (single_pixel >> 1) & 0x0f;
uint8_t single_pixel_A = (single_pixel >> 12) & 0x0f;
uint8_t single_pixel_R = (single_pixel >> 8) & 0x0f;
uint8_t single_pixel_G = (single_pixel >> 4) & 0x0f;
uint8_t single_pixel_B = single_pixel & 0x0f;
if (single_pixel_A != 0x0f) {
single_pixel_R = single_pixel_R * single_pixel_A / 15;
single_pixel_G = single_pixel_G * single_pixel_A / 15;
single_pixel_B = single_pixel_B * single_pixel_A / 15;
}
single_pixel_R |= (single_pixel_R << 4);
single_pixel_G |= (single_pixel_G << 4);
single_pixel_B |= (single_pixel_B << 4);
Expand All @@ -147,8 +153,6 @@ static int generate_png(capture_info_t *capinfo, uint8_t **png, unsigned int *pn
}
}



}
}
unsigned int result = lodepng_encode(png, png_len, png_buffer, (png_width + png_left + png_right), png_height, &state);
Expand Down
4 changes: 2 additions & 2 deletions src/geometry.c
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Original file line number Diff line number Diff line change
Expand Up @@ -62,8 +62,8 @@ static const char *bpp_names[] = {

static param_t params[] = {
{ SETUP_MODE, "Setup Mode", "setup_mode", 0,NUM_SETUP-1, 1 },
{ H_OFFSET, "H Offset", "h_offset", 0, 512, 4 },
{ V_OFFSET, "V Offset", "v_offset", 0, 512, 1 },
{ H_OFFSET, "H Offset", "h_offset", 1, 384, 4 },
{ V_OFFSET, "V Offset", "v_offset", 0, 256, 1 },
{ MIN_H_WIDTH, "Min H Width", "min_h_width", 150, 1920, 8 },
{MIN_V_HEIGHT, "Min V Height", "min_v_height", 150, 1200, 2 },
{ MAX_H_WIDTH, "Max H Width", "max_h_width", 200, 1920, 8 },
Expand Down
171 changes: 64 additions & 107 deletions src/macros.S
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Original file line number Diff line number Diff line change
Expand Up @@ -723,144 +723,94 @@ wait_wr\@:
.endm


.macro SETUP_NINE_BITS_MASK_R14
mov r14, #0x00000018 //2 high order bits of blue (0x0018)
orr r14, r14, #0x0000c700 //3 high order bits of green (0x0700) + 2 high order bit of red (0xc000) //
orr r14, r14, r14, lsl #16 //put in both pixels
tst r3, #BIT_OSD
movne r14, #0
tst r3, #BIT_NO_SCANLINES | BIT_INTERLACED_VIDEO
moveq r14, #0
.macro SETUP_NINELO_BITS_MASK_R14
mov r14, #0x77 << PIXEL_BASE
orr r14, r14, #0x700 << PIXEL_BASE
.endm

.macro CAPTURE_NINELO_BITS_16BPP_LO reg
// Pixel in GPIO 13.. 2 -> 15.. 0
and r9, r8, #0x07 << PIXEL_BASE
eor r10, \reg, r9, lsr #(PIXEL_BASE - 2)
and r12, r8, #0x07 << (PIXEL_BASE + 4)
eor r10, r10, r12, lsl #(4 - PIXEL_BASE)
and r9, r8, #0x07 << (PIXEL_BASE + 8)
eor r10, r10, r9, lsl #(5 - PIXEL_BASE)
and r9, r8, r14
bic r8, r8, r14, lsr #1
eor r10, \reg, r9, lsr #(PIXEL_BASE - 1)
and r8, r8, r14
eor r10, r10, r8, lsr #(PIXEL_BASE + 2)
.endm

.macro CAPTURE_NINELO_BITS_16BPP_HI reg
// Pixel in GPIO 13.. 2 -> 31.. 16
and r9, r8, #0x07 << PIXEL_BASE
eor r10, r10, r9, lsl #(16 - (PIXEL_BASE - 2))
and r12, r8, #0x07 << (PIXEL_BASE + 4)
eor r10, r10, r12, lsl #(16 + (4 - PIXEL_BASE))
and r9, r8, #0x07 << (PIXEL_BASE + 8)
eor r10, r10, r9, lsl #(16 + (5 - PIXEL_BASE))
and r9, r10, r14 // extract high order bits
tst r3, #BIT_OSD
orreq \reg, r10, r9, lsr #3 // put high order bits in unused low order bits to ensure full range 5r 6g 5b
movne \reg, r10, lsr #1 // half intensity for menu (low order bits already 0
and r9, r8, r14
bic r8, r8, r14, lsr #1
eor r10, r10, r9, lsl #(16 - (PIXEL_BASE - 1))
and r8, r8, r14
eor \reg, r10, r8, lsl #(16 - (PIXEL_BASE + 2))
.endm

.macro CAPTURE_NINELO_BITS_DOUBLE_16BPP reg reg2
// Pixel in GPIO 13.. 2 -> 15.. 0
and r9, r8, #0x07 << PIXEL_BASE
eor r10, \reg, r9, lsr #(PIXEL_BASE - 2)
and r12, r8, #0x07 << (PIXEL_BASE + 4)
eor r10, r10, r12, lsl #(4 - PIXEL_BASE)
and r9, r8, #0x07 << (PIXEL_BASE + 8)
eor r10, r10, r9, lsl #(5 - PIXEL_BASE)
// Pixel double
orr r10, r10, r10, lsl #16
and r9, r10, r14 // extract high order bits
tst r3, #BIT_OSD
orreq \reg2, r10, r9, lsr #3 // put high order bits in unused low order bits to ensure full range 5r 6g 5b
movne \reg2, r10, lsr #1 // half intensity for menu (low order bits already 0
and r9, r8, r14
bic r8, r8, r14, lsr #1
eor r10, \reg, r9, lsr #(PIXEL_BASE - 1)
and r8, r8, r14
eor r10, r10, r8, lsr #(PIXEL_BASE + 2)
eor \reg2, r10, r10, lsl #16
.endm

.macro SETUP_NINEHI_BITS_MASK_R14
mov r14, #0xee << PIXEL_BASE
orr r14, r14, #0xe00 << PIXEL_BASE
.endm

.macro CAPTURE_NINEHI_BITS_16BPP_LO reg
// Pixel in GPIO 13.. 2 -> 15.. 0
and r9, r8, #0x0e << PIXEL_BASE
eor r10, \reg, r9, lsr #(PIXEL_BASE - 1)
and r12, r8, #0x0e << (PIXEL_BASE + 4)
eor r10, r10, r12, lsl #(3 - PIXEL_BASE)
and r9, r8, #0x0e << (PIXEL_BASE + 8)
eor r10, r10, r9, lsl #(4 - PIXEL_BASE)
and r9, r8, r14
bic r8, r8, r14, lsr #1
eor r10, \reg, r9, lsr #PIXEL_BASE
and r8, r8, r14
eor r10, r10, r8, lsr #(PIXEL_BASE + 3)
.endm

.macro CAPTURE_NINEHI_BITS_16BPP_HI reg
// Pixel in GPIO 13.. 2 -> 31.. 16
and r9, r8, #0x0e << PIXEL_BASE
eor r10, r10, r9, lsl #(16 - (PIXEL_BASE - 1))
and r12, r8, #0x0e << (PIXEL_BASE + 4)
eor r10, r10, r12, lsl #(16 + (3 - PIXEL_BASE))
and r9, r8, #0x0e << (PIXEL_BASE + 8)
eor r10, r10, r9, lsl #(16 + (4 - PIXEL_BASE))
and r9, r10, r14 // extract high order bits
tst r3, #BIT_OSD
orreq \reg, r10, r9, lsr #3 // put high order bits in unused low order bits to ensure full range 5r 6g 5b
movne \reg, r10, lsr #1 // half intensity for menu (low order bits already 0
and r9, r8, r14
bic r8, r8, r14, lsr #1
eor r10, r10, r9, lsl #(16 - PIXEL_BASE)
and r8, r8, r14
eor \reg, r10, r8, lsl #(16 - (PIXEL_BASE + 3))
.endm

.macro CAPTURE_NINEHI_BITS_DOUBLE_16BPP reg reg2
// Pixel in GPIO 13.. 2 -> 15.. 0
and r9, r8, #0x0e << PIXEL_BASE
eor r10, \reg, r9, lsr #(PIXEL_BASE - 1)
and r12, r8, #0x0e << (PIXEL_BASE + 4)
eor r10, r10, r12, lsl #(3 - PIXEL_BASE)
and r9, r8, #0x0e << (PIXEL_BASE + 8)
eor r10, r10, r9, lsl #(4 - PIXEL_BASE)
// Pixel double
orr r10, r10, r10, lsl #16
and r9, r10, r14 // extract high order bits
tst r3, #BIT_OSD
orreq \reg2, r10, r9, lsr #3 // put high order bits in unused low order bits to ensure full range 5r 6g 5b
movne \reg2, r10, lsr #1 // half intensity for menu (low order bits already 0
and r9, r8, r14
bic r8, r8, r14, lsr #1
eor r10, \reg, r9, lsr #PIXEL_BASE
and r8, r8, r14
eor r10, r10, r8, lsr #(PIXEL_BASE + 3)
eor \reg2, r10, r10, lsl #16
.endm

.macro SETUP_TWELVE_BITS_MASK_R14
mov r14, #0x00000610 //2 high order bits of green (0x0600) + 1 high order bit of blue (0x0010)
orr r14, r14, #0x00008000 //1 high order bit of red (0x8000)
orr r14, r14, r14, lsl #16 //put in both pixels
tst r3, #BIT_OSD
movne r14, #0
tst r3, #BIT_NO_SCANLINES | BIT_INTERLACED_VIDEO
moveq r14, #0
mov r14, #0xff << PIXEL_BASE
orr r14, r14, #0xf00 << PIXEL_BASE
.endm

.macro CAPTURE_TWELVE_BITS_16BPP_LO reg
// Pixel in GPIO 13.. 2 -> 15.. 0
and r9, r8, #0x0f << PIXEL_BASE
eor r10, \reg, r9, lsr #(PIXEL_BASE - 1)
and r12, r8, #0x0f << (PIXEL_BASE + 4)
eor r10, r10, r12, lsl #(3 - PIXEL_BASE)
and r9, r8, #0x0f << (PIXEL_BASE + 8)
eor r10, r10, r9, lsl #(4 - PIXEL_BASE)
and r9, r8, r14
eor r10, \reg, r9, lsr #(PIXEL_BASE)
.endm

.macro CAPTURE_TWELVE_BITS_16BPP_HI reg
// Pixel in GPIO 13.. 2 -> 31.. 16
and r9, r8, #0x0f << PIXEL_BASE
eor r10, r10, r9, lsl #(16 - (PIXEL_BASE - 1))
and r12, r8, #0x0f << (PIXEL_BASE + 4)
eor r10, r10, r12, lsl #(16 + (3 - PIXEL_BASE))
and r9, r8, #0x0f << (PIXEL_BASE + 8)
eor r10, r10, r9, lsl #(16 + (4 - PIXEL_BASE))
and r9, r10, r14 // extract high order bits
tst r3, #BIT_OSD
orreq \reg, r10, r9, lsr #4 // put high order bits in unused low order bits to ensure full range 5r 6g 5b
movne \reg, r10, lsr #1 // half intensity for menu (low order bits already 0
and r9, r8, r14
eor \reg, r10, r9, lsl #(16 - PIXEL_BASE)
.endm

.macro CAPTURE_TWELVE_BITS_DOUBLE_16BPP reg reg2
// Pixel in GPIO 13.. 2 -> 15.. 0
and r9, r8, #0x0f << PIXEL_BASE
eor r10, \reg, r9, lsr #(PIXEL_BASE - 1)
and r12, r8, #0x0f << (PIXEL_BASE + 4)
eor r10, r10, r12, lsl #(3 - PIXEL_BASE)
and r9, r8, #0x0f << (PIXEL_BASE + 8)
eor r10, r10, r9, lsl #(4 - PIXEL_BASE)
// Pixel double
orr r10, r10, r10, lsl #16
and r9, r10, r14 // extract high order bits
tst r3, #BIT_OSD
orreq \reg2, r10, r9, lsr #4 // put high order bits in unused low order bits to ensure full range 5r 6g 5b
movne \reg2, r10, lsr #1 // half intensity for menu (low order bits already 0
and r9, r8, r14
eor r10, \reg, r9, lsr #(PIXEL_BASE)
eor \reg2, r10, r10, lsl #16
.endm

.macro CAPTURE_LOW_BITS_TRANSLATE
Expand Down Expand Up @@ -1074,17 +1024,23 @@ wait_wr\@:
.endm

.macro SETUP_VSYNC_DEBUG_16BPP_R11
tst r3, #BIT_OSD
ldreq r11, =#0xf000f000
ldrne r11, =#0x70007000
tst r3, #BIT_VSYNC_MARKER
ldrne r11, =0xe000e000
moveq r11, #0
eorne r11, r11, #0x0f000000
eorne r11, r11, #0x00000f00
tst r3, #BIT_NO_SCANLINES | BIT_INTERLACED_VIDEO
ldreq r12, =param_intensity
ldreq r12, [r12]
.endm

.macro WRITE_R5_R6_IF_LAST_16BPP
cmp r1, #1
stmeqia r0, {r5, r6}
tsteq r3, #BIT_NO_SCANLINES | BIT_INTERLACED_VIDEO
moveq r5, r5, lsr #1
moveq r6, r6, lsr #1
eoreq r5, r5, r12
eoreq r6, r6, r12
cmp r1, #1
tsteq r3, #BIT_NO_LINE_DOUBLE
subeq r0, r0, r2
Expand All @@ -1094,10 +1050,11 @@ wait_wr\@:
.macro WRITE_R5_R6_R7_R10_16BPP
stmia r0, {r5, r6, r7, r10}
tst r3, #BIT_NO_SCANLINES | BIT_INTERLACED_VIDEO
moveq r5, r5, lsr #1
moveq r6, r6, lsr #1
moveq r7, r7, lsr #1
moveq r10, r10, lsr #1
eoreq r5, r5, r12
eoreq r6, r6, r12
eoreq r7, r7, r12
eoreq r10, r10, r12

tst r3, #BIT_NO_LINE_DOUBLE
subeq r0, r0, r2
stmeqia r0, {r5, r6, r7, r10}
Expand Down
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