design_db: a verification-gated library of subcircuit implementations#5

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Commits on Jul 2, 2026

design_db: content-addressed store of verification-gated implementations (S1 core)
Felix Arnold
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design_db: selection engine, @from_design_db decorator, spire db CLI (S2)
Felix Arnold
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added seed with original design
Felix Arnold
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updated design db md
Felix Arnold
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S3 phase done
Felix Arnold
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Commits on Jul 6, 2026

added --check flag to verify
Felix Arnold
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design_db: self-describing metric systems + `annotate` enrichment, permanent slot
Felix Arnold
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python (spire) designs as first-class inserts — source stored, Verilog stays the IR
Felix Arnold
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Commits on Jul 7, 2026

design_db: derive the per-slot index from designs/ (atomic-admit source of truth; index.json = self-healing cache; fcntl-locked manifest) â concurrent inserts can never lose designs
Felix Arnold
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Commits on Jul 8, 2026

updated design db readme with fill hook contract
Felix Arnold
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added design db to main readme
Felix Arnold
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design_db: gate works without EDA binaries; pyosys child fallback + yosys equiv C.
Felix Arnold
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small ref update in readme due to rtlscout change
Felix Arnold
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Commits on Jul 9, 2026

design db readme update
Felix Arnold
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design_db: temporary selection overrides (env + context manager, never recorded); readers never create; identifier docs clarified
Felix Arnold
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design_db: pick_design (pure query), compile-scoped selection log, temporary selection overrides

Felix Arnold
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claude
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