- The project aims to design a 10-bit Potentiometric Digital to Analog Converter using end-to-end Synopsys Commercial EDA tool(Custom Complier). The target is to design 10-bit potentiometric DAC with 1.8v digital voltage and 1 off-chip external voltage reference using SAED_PDK 28_32nm technology node
- Introduction
- EDA tools used to implement Potentiometric DAC
- Architecture
- IP Design Specifications
- Implementation of 10Bit Potentiometric DAC
- Pre-layout Designs
- References
- Contributor
- Acknowledgments
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In real world, most of the data available is in the form of analog in nature. We have two types of converters analog to digital converter and digital to analog converter. These two converting interfaces are essential to obtain the required operations of a processor to manipulate the data of digital electronic equipment and an analog electric equipment. Digital to Analog Converter (DAC) is a device that transforms digital data into an analog signal in order to interact with the real world. The digital signal is represented with a binary code, which is a combination of bits 0’s and 1’s. The digital data can be produced from a microprocessor, Field Programmable Gate Array (FPGA), or Application Specified Integrated Circuit (ASIC). There are two commonly used DAC conversions – Weighed resistors method and R-2R ladder network method. Applications of a DAC: audio amplifier, video encoder, display electronics, data acquisition systems, calibration, Digital potentiometer.
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A n-bit Digital to Analog Converter (DAC) takes a n-bit digital word and converts it into a proportional analog voltage with respect to the reference voltage. The potentiometric DAC uses the concept of Voltage Divider. In an N-bit DAC, the analog voltage range, i.e. the Vref (here 1.8 V) is equally divided into 2^N voltage values. This is achieved by a series on 2^N equal resistors and taps are provided across each R. The combination of switches to tap the values is designed using the N-bit digital word as input. An example of N-bit potentiometric DAC is shown in the figure below.
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Two types of DACs :
- Weighted Resistor DAC
- R-2R Ladder DAC
- A weighted resistor DAC produces an analog output, which is almost equal to the digital (binary) input by using binary weighted resistors in the inverting adder circuit. In short, a binary weighted resistor DAC is called as weighted resistor DAC.
- The R-2R Ladder DAC overcomes the disadvantages of a binary weighted resistor DAC. As the name suggests, R-2R Ladder DAC produces an analog output, which is almost equal to the digital (binary) input by using a R-2R ladder network in the inverting adder circuit.
The switches are designed as shown in the figure above. The digital voltage of 1.8V or 0V is given at the digital input port for logic 1 and 0 respectively. If the digital input is logic 1, then Vin1 appears at the output port, else Vin2 appears at the output. Hence this switch circuit replaces two switches in same level as it takes into account both the swiches of complemented and uncomplemented bit.
- The design has been built using Commericial EDA tools like Synopsys Custom Compiler. The library used is SAED32_28nm.
- This design is implemented using
- Custom Compiler
- Prime wave
- IC validator
- HSPICE
| Name | I/O | Description |
|---|---|---|
| D [0:9] | I | Digital inputs |
| VOUT | O | DAC analog voltage output |
| VDDA | I | Analog voltage supply (1.8) |
| VSSA | I | Analog ground 0V |
| VREFH | I | Reference voltage low for DAC |
The basic idea is to divide the voltage into N different voltage values in the range of VREFH and VREFL- for an N-Bit DAC. The design used here to achieve this is the simple resistor string DAC which consists of resistors in series. These resistors are then connected to various switches in such a fashion that it routes the exact voltage to the output. The problem of the largeness of the circuit is reduced by building hierarchical subcircuits of 10-Bit potentiometric DAC – Switch, 2-bit, 3-bit, 4-bit, 5-bit, 6-bit, 7-bit, 8-bit, 9-bit and 10-bit.
| Name | Value | Description |
|---|---|---|
| D_in | v1 = 0V, v2 = 1.05V, tr = 0.1us | Digital inputs |
| Capacitor | 1pf | DAC analog voltage output |
| VDDA | 1.8v | Analog voltage supply (1.8v) |
| VSSA | 0v | Analog ground 0V |
| VREFH | 1.2v | Reference voltage High for DAC |
| VREFL | 0.8v | Reference voltage low for DAC |
| Name | Value | Description |
|---|---|---|
| D_in | v1 = 0V, v2 = 1.05V, tr = 0.1us | Digital inputs |
| Resistor | 200ohms | Resistance |
| Capacitor | 5pf | Capacitance |
| VDDA | 1.8v | Analog voltage supply (1.8v) |
| VSSA | 0v | Analog ground 0V |
| VREFH | 1.2v | Reference voltage High for DAC |
| VREFL | 0.8v | Reference voltage low for DAC |
- 2-Bit DAC is implemented using 3 switch instances. 2-Bit circuitry and waveform are shown below
- For the 2 bit DAC, switch circuit was included as a subcircuit. After creating the schematics, the spice netlist was extracted. The necessary model files of SAED32nm tt transistors were included in the netlist and transient analysis was performed.
- 3Bit DAC is implemented using 2 2-Bit DACs and 1 switch instances. 3-Bit circuitry and waveform are shown below
- 4Bit DAC is implemented using 2 and 3-Bit DACs and 1 switch instances. 4-Bit circuitry and waveform are shown below
- 5Bit DAC is implemented using 2 and 4-Bit DACs and 1 switch instances. 5-Bit circuitry and waveform are shown below
- 6Bit DAC is implemented using 2 and 5-Bit DACs and 1 switch instances. 6-Bit circuitry and waveform are shown below
- 7Bit DAC is implemented using 2 and 6-Bit DACs and 1 switch instances. 7-Bit circuitry and waveform are shown below
- 8Bit DAC is implemented using 2 and 7-Bit DACs and 1 switch instances. 8-Bit circuitry and waveform are shown below
- 9Bit DAC is implemented using 2 and 8-Bit DACs and 1 switch instances. 9-Bit circuitry and waveform are shown below
- 10Bit DAC is implemented using 2 and 9-Bit DACs and 1 switch instances. 10-Bit circuitry and waveform are shown below
- For 3 Bit DAC : D0, D1 and D2
- For 4 Bit DAC : D0, D1, D2 and D3 and so on.
- For 10 Bit DAC : D0, D1, D2...., D9.
- Other Inputs value remains the same as 2 Bit DAC until 10 Bit DAC.
- For 2 Bit DAC, Number of steps in the output graph = 2^N, i.e, 2^2 = 4 steps
- For a 10 Bit DAC, Number of steps in the output graph = 2^N, i.e, 2^10 = 1024 steps.
- The graph value for DAC ranges from VrefH (1.8V) to VrefL (0V).
- Need to start with custom layout stimulations for DAC Layout
- Sammer Duroji VSD team
- Kanna Shalini VSD team
- Skandha Deepsita VSD team
- Aakash.K
Contact:[email protected] - Kunal Ghosh, Co-founder, VLSI SYSTEM DESIGN (VSD) Corp Pvt.Ltd - [email protected]
- Kunal Ghosh, Co-founder, VLSI SYSTEM DESIGN (VSD) Corp Pvt.Ltd - [email protected]
- Muthukrishnan Chinnasamy, CEO of Semiconductor Fabless Accelerator Lab(SFAL)
- Montu Makadia - Semiconductor Fabless Accelerator Lab (SFAL)