add R-V V build check

Signed-off-by: sunyuechi <[email protected]>
intel · Feb 27, 2025 · 8c65861 · 8c65861
1 parent d2b37b1
commit 8c65861
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Showing 4 changed files with 46 additions and 12 deletions.
diff --git a/configure.ac b/configure.ac
@@ -39,16 +39,41 @@ AM_CONDITIONAL([CPU_AARCH64], [test "$CPU" = "aarch64"])
 AM_CONDITIONAL([CPU_PPC64LE], [test "$CPU" = "ppc64le"])
 AM_CONDITIONAL([CPU_RISCV64], [test "$CPU" = "riscv64"])
 AM_CONDITIONAL([CPU_UNDEFINED], [test "x$CPU" = "x"])
+AM_CONDITIONAL([HAVE_RVV], [false])
 
-if test "$CPU" = "x86_64"; then
-   is_x86=yes
-else
-   if test "$CPU" = "x86_32"; then
-      is_x86=yes
-   else
-      is_x86=no
-   fi
-fi
+case "${CPU}" in
+
+	x86_64)
+
+		is_x86=yes
+		;;
+
+	x86_32)
+
+		is_x86=yes
+		;;
+
+	riscv64)
+
+		AC_MSG_CHECKING([checking RVV support])
+		AC_COMPILE_IFELSE(
+			[AC_LANG_PROGRAM([], [
+				__asm__ volatile(
+					".option arch, +v\n"
+					"vsetivli zero, 0, e8, m1, ta, ma\n"
+				);
+			])],
+			[AC_DEFINE([HAVE_RVV], [1], [Enable RVV instructions])
+			AM_CONDITIONAL([HAVE_RVV], [true]) rvv=yes],
+			[AM_CONDITIONAL([HAVE_RVV], [false]) rvv=no]
+		)
+		AC_MSG_RESULT([$rvv])
+		;;
+
+	*)
+		is_x86=no
+
+esac
 
 # Check for programs
 AC_PROG_CC_STDC

diff --git a/igzip/riscv64/Makefile.am b/igzip/riscv64/Makefile.am
@@ -29,5 +29,8 @@
 
 lsrc_riscv64 += \
 	igzip/riscv64/igzip_multibinary_riscv64_dispatcher.c \
-	igzip/riscv64/igzip_multibinary_riscv64.S \
-	igzip/riscv64/igzip_isal_adler32_rvv.S
+	igzip/riscv64/igzip_multibinary_riscv64.S
+
+if HAVE_RVV
+lsrc_riscv64 += igzip/riscv64/igzip_isal_adler32_rvv.S
+endif
diff --git a/igzip/riscv64/igzip_multibinary_riscv64.S b/igzip/riscv64/igzip_multibinary_riscv64.S
@@ -29,7 +29,11 @@
 
 #include "riscv64_multibinary.h"
 
-mbin_interface		isal_adler32
+#if HAVE_RVV
+    mbin_interface		isal_adler32
+#else
+    mbin_interface_base		isal_adler32, adler32_base
+#endif
 
 mbin_interface_base gen_icf_map_lh1, gen_icf_map_h1_base
 mbin_interface_base decode_huffman_code_block_stateless, decode_huffman_code_block_stateless_base

diff --git a/igzip/riscv64/igzip_multibinary_riscv64_dispatcher.c b/igzip/riscv64/igzip_multibinary_riscv64_dispatcher.c
@@ -30,9 +30,11 @@
 
 DEFINE_INTERFACE_DISPATCHER(isal_adler32)
 {
+#if HAVE_RVV
         const unsigned long hwcap = getauxval(AT_HWCAP);
         if (hwcap & HWCAP_RV('V'))
                 return PROVIDER_INFO(adler32_rvv);
         else
+#endif
                 return PROVIDER_BASIC(adler32);
 }