Add RISC-V V extension support and add R-V V isal_adler32

.clang-format-ignore

@@ -1,3 +1,6 @@
 include/aarch64_multibinary.h
 include/aarch64_label.h
 **/aarch64/*.h
+
+include/riscv64_multibinary.h
+**/riscv64/*.h

Makefile.am

@@ -29,10 +29,12 @@ other_tests_x86_64=
 other_tests_x86_32=
 other_tests_aarch64=
 other_tests_ppc64le=
+other_tests_riscv64=
 lsrc_x86_64=
 lsrc_x86_32=
 lsrc_aarch64=
 lsrc_ppc64le=
+lsrc_riscv64=
 lsrc_base_aliases=
 lsrc32=
 unit_tests32=
@@ -83,6 +85,12 @@ libisal_la_SOURCES += ${lsrc_ppc64le}
 other_tests += ${other_tests_ppc64le}
 endif
 
+if CPU_RISCV64
+ARCH=-Driscv64
+libisal_la_SOURCES += ${lsrc_riscv64}
+other_tests += ${other_tests_riscv64}
+endif
+
 if CPU_UNDEFINED
 libisal_la_SOURCES += ${lsrc_base_aliases}
 endif
@@ -131,6 +139,9 @@ endif
 if CPU_AARCH64
   as_filter = $(CC) -D__ASSEMBLY__
 endif
+if CPU_RISCV64
+  as_filter = $(CC) -D__ASSEMBLY__
+endif
 
 CCAS = $(as_filter)
 EXTRA_DIST += tools/yasm-filter.sh tools/nasm-filter.sh
@@ -142,6 +153,9 @@ AM_CCASFLAGS = ${AM_CFLAGS}
 else
 AM_CCASFLAGS = ${yasm_args} ${INCLUDE} ${src_include} ${DEFS} ${D}
 endif
+if CPU_RISCV64
+AM_CCASFLAGS = ${AM_CFLAGS}
+endif
 
 .asm.s:
 	@echo "  MKTMP   " $@;

configure.ac

@@ -31,22 +31,15 @@ AS_CASE([$host_cpu],
   [arm64], [CPU="aarch64"],
   [powerpc64le], [CPU="ppc64le"],
   [ppc64le], [CPU="ppc64le"],
+  [riscv64], [CPU="riscv64"],
 )
 AM_CONDITIONAL([CPU_X86_64], [test "$CPU" = "x86_64"])
 AM_CONDITIONAL([CPU_X86_32], [test "$CPU" = "x86_32"])
 AM_CONDITIONAL([CPU_AARCH64], [test "$CPU" = "aarch64"])
 AM_CONDITIONAL([CPU_PPC64LE], [test "$CPU" = "ppc64le"])
+AM_CONDITIONAL([CPU_RISCV64], [test "$CPU" = "riscv64"])
 AM_CONDITIONAL([CPU_UNDEFINED], [test "x$CPU" = "x"])
-
-if test "$CPU" = "x86_64"; then
-   is_x86=yes
-else
-   if test "$CPU" = "x86_32"; then
-      is_x86=yes
-   else
-      is_x86=no
-   fi
-fi
+AM_CONDITIONAL([HAVE_RVV], [false])
 
 # Check for programs
 AC_PROG_CC_STDC
@@ -57,6 +50,40 @@ AC_PREFIX_DEFAULT([/usr])
 AC_PROG_SED
 AC_PROG_MKDIR_P
 
+case "${CPU}" in
+
+	x86_64)
+
+		is_x86=yes
+		;;
+
+	x86_32)
+
+		is_x86=yes
+		;;
+
+	riscv64)
+
+		AC_MSG_CHECKING([checking RVV support])
+		AC_COMPILE_IFELSE(
+			[AC_LANG_PROGRAM([], [
+				__asm__ volatile(
+					".option arch, +v\n"
+					"vsetivli zero, 0, e8, m1, ta, ma\n"
+				);
+			])],
+			[AC_DEFINE([HAVE_RVV], [1], [Enable RVV instructions])
+			AM_CONDITIONAL([HAVE_RVV], [true]) rvv=yes],
+			[AM_CONDITIONAL([HAVE_RVV], [false]) rvv=no]
+		)
+		AC_MSG_RESULT([$rvv])
+		;;
+
+	*)
+		is_x86=no
+
+esac
+
 # Options
 AC_ARG_ENABLE([debug],
         AS_HELP_STRING([--enable-debug], [enable debug messages @<:@default=disabled@:>@]),

crc/Makefile.am

@@ -36,6 +36,7 @@ lsrc  += \
 lsrc_base_aliases += crc/crc_base_aliases.c
 lsrc_x86_32       += crc/crc_base_aliases.c
 lsrc_ppc64le      += crc/crc_base_aliases.c
+lsrc_riscv64      += crc/crc_base_aliases.c
 
 lsrc_x86_64 += \
 	crc/crc16_t10dif_01.asm \

erasure_code/Makefile.am

@@ -34,6 +34,7 @@ include erasure_code/ppc64le/Makefile.am
 lsrc         += erasure_code/ec_base.c
 
 lsrc_base_aliases += erasure_code/ec_base_aliases.c
+lsrc_riscv64      += erasure_code/ec_base_aliases.c
 lsrc_x86_64  += \
 		erasure_code/ec_highlevel_func.c \
 		erasure_code/gf_vect_mul_sse.asm \

igzip/Makefile.am

@@ -27,6 +27,8 @@
 #  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 ########################################################################
 
+include igzip/riscv64/Makefile.am
+
 lsrc        += 	igzip/igzip.c \
 		igzip/hufftables_c.c \
 		igzip/igzip_base.c \
@@ -39,6 +41,7 @@ lsrc        += 	igzip/igzip.c \
 lsrc_base_aliases += igzip/igzip_base_aliases.c igzip/proc_heap_base.c
 lsrc_x86_32       += igzip/igzip_base_aliases.c igzip/proc_heap_base.c
 lsrc_ppc64le      += igzip/igzip_base_aliases.c igzip/proc_heap_base.c
+lsrc_riscv64      +=                            igzip/proc_heap_base.c
 
 lsrc_aarch64 +=	igzip/aarch64/igzip_inflate_multibinary_arm64.S  \
 		igzip/aarch64/igzip_multibinary_arm64.S	\

igzip/checksum32_funcs_test.c

@@ -126,7 +126,7 @@ main(int argc, char *argv[])
 int
 zeros_test(func_case_t *test_func)
 {
-        uint32_t c_dut, c_ref;
+        volatile uint32_t c_dut, c_ref;
         int fail = 0;
         unsigned char *buf = NULL;
 
@@ -153,7 +153,7 @@ zeros_test(func_case_t *test_func)
 int
 simple_pattern_test(func_case_t *test_func)
 {
-        uint32_t c_dut, c_ref;
+        volatile uint32_t c_dut, c_ref;
         int fail = 0;
         unsigned char *buf = NULL;
 
@@ -176,7 +176,7 @@ simple_pattern_test(func_case_t *test_func)
 int
 seeds_sizes_test(func_case_t *test_func)
 {
-        uint32_t c_dut, c_ref;
+        volatile uint32_t c_dut, c_ref;
         int fail = 0;
         int i;
         uint32_t r, s;
@@ -251,7 +251,7 @@ seeds_sizes_test(func_case_t *test_func)
 int
 eob_test(func_case_t *test_func)
 {
-        uint32_t c_dut, c_ref;
+        volatile uint32_t c_dut, c_ref;
         int fail = 0;
         int i;
         unsigned char *buf = NULL;
@@ -277,7 +277,7 @@ eob_test(func_case_t *test_func)
 int
 update_test(func_case_t *test_func)
 {
-        uint32_t c_dut, c_ref;
+        volatile uint32_t c_dut, c_ref;
         int fail = 0;
         int i;
         uint32_t r;
@@ -310,7 +310,7 @@ update_test(func_case_t *test_func)
 int
 update_over_mod_test(func_case_t *test_func)
 {
-        uint32_t c_dut, c_ref;
+        volatile uint32_t c_dut, c_ref;
         int fail = 0;
         int i;
         unsigned char *buf = NULL;

igzip/riscv64/Makefile.am

@@ -0,0 +1,33 @@
+########################################################################
+#  Copyright (c) 2025 Institute of Software Chinese Academy of Sciences (ISCAS).
+#
+#  Redistribution and use in source and binary forms, with or without
+#  modification, are permitted provided that the following conditions
+#  are met:
+#    * Redistributions of source code must retain the above copyright
+#      notice, this list of conditions and the following disclaimer.
+#    * Redistributions in binary form must reproduce the above copyright
+#      notice, this list of conditions and the following disclaimer in
+#      the documentation and/or other materials provided with the
+#      distribution.
+#    * Neither the name of ISCAS Corporation nor the names of its
+#      contributors may be used to endorse or promote products derived
+#      from this software without specific prior written permission.
+#
+#  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+#  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+#  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+#  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+#  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+#  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+#  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+#  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+#  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+#  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+#  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+########################################################################
+
+lsrc_riscv64 += \
+	igzip/riscv64/igzip_multibinary_riscv64_dispatcher.c \
+	igzip/riscv64/igzip_multibinary_riscv64.S \
+	igzip/riscv64/igzip_isal_adler32_rvv.S

igzip/riscv64/igzip_isal_adler32_rvv.S

@@ -0,0 +1,78 @@
+/**********************************************************************
+  Copyright (c) 2025 Institute of Software Chinese Academy of Sciences (ISCAS).
+
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions
+  are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in
+      the documentation and/or other materials provided with the
+      distribution.
+    * Neither the name of ISCAS Corporation nor the names of its
+      contributors may be used to endorse or promote products derived
+      from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**********************************************************************/
+#if HAVE_RVV
+.option         arch, +v
+.global         adler32_rvv
+.type           adler32_rvv, %function
+adler32_rvv:
+  slli          t2, a0, 48
+  srli          t2, t2, 48                           // t2: A = adler32 & 0xffff;
+  srliw         t3, a0, 16                           // t3: B = adler32 >> 16;
+  beqz          a2, 2f
+
+  vsetvli       zero, a2, e64, m8, tu, ma
+  vmv.v.i       v8, 0
+  vmv.v.i       v16, 0
+  vmv.s.x       v24, zero
+  mv            t6, a2                               // t6 = length
+  vsetvli       zero, zero, e32, m4, tu, ma
+  vmv.s.x       v8, t2                               // v8 = adler32 & 0xffff
+
+1:
+  vsetvli       t1, a2, e8, m1, tu, ma
+  vle8.v        v0, (a1)
+  vsetvli       zero, zero, e32, m4, tu, ma
+  vzext.vf4     v4, v0
+  vid.v         v12                                  // 0, 1, 2, .. vl-1
+  vadd.vv       v8, v8, v4
+  vrsub.vx      v12, v12, a2                         // len, len-1, len-2
+  vwmaccu.vv    v16, v12, v4                         // v16: B += weight * next
+  sub           a2, a2, t1
+  add           a1, a1, t1
+  bnez          a2, 1b
+
+  vsetvli       zero, t6, e32, m4, tu, ma
+  vwredsumu.vs  v24, v8, v24
+  mul           a7, t6, t2                           // B += A(init) * len
+  vsetvli       zero, t6, e64, m8, tu, ma
+  vmv.s.x       v0, a7
+  vredsum.vs    v0, v16, v0
+  vmv.x.s       t4, v0                               // B = t4
+  vmv.x.s       t2, v24                              // A = t2
+  add           t3, t4, t3
+
+2:
+  li            t0, 65521
+  remu          t2, t2, t0                           // A = A % ADLER_MOD
+  remu          t3, t3, t0                           // B = B % ADLER_MOD
+  slli          t3, t3, 16                           // B << 16
+  add           a0, t2, t3                           // a0 = A + B
+
+  ret
+#endif

igzip/riscv64/igzip_multibinary_riscv64.S

@@ -0,0 +1,54 @@
+/**********************************************************************
+  Copyright (c) 2025 Institute of Software Chinese Academy of Sciences (ISCAS).
+
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions
+  are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in
+      the documentation and/or other materials provided with the
+      distribution.
+    * Neither the name of ISCAS Corporation nor the names of its
+      contributors may be used to endorse or promote products derived
+      from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**********************************************************************/
+
+#include "riscv64_multibinary.h"
+
+#if HAVE_RVV
+    mbin_interface		isal_adler32
+#else
+    mbin_interface_base		isal_adler32, adler32_base
+#endif
+
+mbin_interface_base gen_icf_map_lh1, gen_icf_map_h1_base
+mbin_interface_base decode_huffman_code_block_stateless, decode_huffman_code_block_stateless_base
+mbin_interface_base isal_deflate_icf_finish_lvl3, isal_deflate_icf_finish_hash_map_base
+mbin_interface_base isal_deflate_hash_lvl3, isal_deflate_hash_base
+mbin_interface_base isal_deflate_hash_lvl1, isal_deflate_hash_base
+mbin_interface_base isal_deflate_icf_body_lvl2, isal_deflate_icf_body_hash_hist_base
+mbin_interface_base isal_deflate_icf_finish_lvl1, isal_deflate_icf_finish_hash_hist_base
+mbin_interface_base isal_deflate_finish, isal_deflate_finish_base
+mbin_interface_base isal_deflate_body, isal_deflate_body_base
+mbin_interface_base isal_deflate_hash_lvl2, isal_deflate_hash_base
+mbin_interface_base encode_deflate_icf, encode_deflate_icf_base
+mbin_interface_base set_long_icf_fg, set_long_icf_fg_base
+mbin_interface_base isal_deflate_icf_body_lvl3, icf_body_hash1_fillgreedy_lazy
+mbin_interface_base isal_deflate_icf_body_lvl1, isal_deflate_icf_body_hash_hist_base
+mbin_interface_base isal_deflate_hash_lvl0, isal_deflate_hash_base
+mbin_interface_base isal_deflate_icf_finish_lvl2, isal_deflate_icf_finish_hash_hist_base
+mbin_interface_base isal_update_histogram, isal_update_histogram_base