hot patch for errors

rmm/src/pmu.rs

@@ -6,6 +6,11 @@ pub const MAX_EVCNT: usize = 31;
 
 #[allow(non_upper_case_globals)]
 const FEAT_PMUv3p7: u64 = 7;
+#[cfg(not(feature = "qemu"))]
+const PMU_MIN_VER: u64 = FEAT_PMUv3p7;
+#[cfg(feature = "qemu")]
+const PMU_MIN_VER: u64 = 5; // FEAT_PMUv3p5
+
 // ID_AA64DFR0_EL1
 // HPMN0, bits [63:60] :
 // Zero PMU event counters for a Guest operating system.
@@ -16,7 +21,7 @@ pub fn pmu_present() -> bool {
         "PMUVer: v3p{:?}",
         ID_AA64DFR0_EL1.read(ID_AA64DFR0_EL1::PMUVer)
     );
-    ID_AA64DFR0_EL1.read(ID_AA64DFR0_EL1::PMUVer) >= FEAT_PMUv3p7
+    ID_AA64DFR0_EL1.read(ID_AA64DFR0_EL1::PMUVer) >= PMU_MIN_VER
 }
 
 pub fn hpmn0_present() -> bool {

rmm/src/rec/simd.rs

@@ -13,7 +13,7 @@ use crate::granule::GranuleState;
 use crate::realm::rd::Rd;
 use crate::rec::RecAuxIndex;
 use crate::rmi::error::Error;
-use crate::simd::{sme_en, SimdConfig, ZCR_EL2_LEN_WIDTH};
+use crate::simd::{sme_en, SimdConfig, MAX_VQ};
 use crate::{get_granule, get_granule_if};
 
 // SIMD context structure
@@ -75,14 +75,15 @@ lazy_static! {
 // SVE registers
 const NUM_VECTOR_REGS: usize = 32;
 const NUM_PREDICATE_REGS: usize = 16;
+
 #[derive(Default, Debug)]
 pub struct SveRegs {
     // lower 128bits of each z register are shared with v
     // implementation-defined lengh: 128bits~2048bits. get it from zcr_el2
-    pub z: [[u128; NUM_VECTOR_REGS]; ZCR_EL2_LEN_WIDTH as usize],
+    pub z: [[u128; NUM_VECTOR_REGS]; MAX_VQ as usize],
     // Each predicate register is 1/8 of the Zx length.
-    pub p: [[u16; NUM_PREDICATE_REGS]; ZCR_EL2_LEN_WIDTH as usize],
-    pub ffr: u64,
+    pub p: [[u16; NUM_PREDICATE_REGS]; MAX_VQ as usize],
+    pub ffr: [u16; MAX_VQ as usize],
     pub zcr_el2: u64,
     pub zcr_el12: u64,
 }
@@ -189,7 +190,7 @@ pub unsafe fn restore_fpu(fpu: &FpuRegs) {
     let addr_q: u64 = fpu.q.as_ptr() as u64;
     unsafe {
         asm!(
-             "ldp q0, q1, [x0]",
+             "ldp q0, q1, [{addr_q}]",
              "ldp q2, q3, [{addr_q}, #32]",
              "ldp q4, q5, [{addr_q}, #64]",
              "ldp q6, q7, [{addr_q}, #96]",

rmm/src/simd.rs

@@ -7,9 +7,18 @@ use lazy_static::lazy_static;
 // Vector length (VL) = size of a Z-register in bytes
 // Vector quadwords (VQ) = size of a Z-register in units of 128 bits
 // Minimum length of a SVE vector: 128 bits
-pub const ZCR_EL2_LEN_WIDTH: u64 = 4;
+const ZCR_EL2_LEN_WIDTH: u64 = 4;
 const SVE_VQ_ARCH_MAX: u64 = (1 << ZCR_EL2_LEN_WIDTH) - 1;
 const QUARD_WORD: u64 = 128;
+// Note: Limit maximun vq to 4 to avoid exceeding a page boundary.
+// Currunt rmm implmentation maps a physical page to a virtual address
+// using its physical address (i.e. identical mapping).
+// Discontiguous Aux granules cannot not be accessed contiguously
+// in their virtual address. For this reason, limit vq up to 4(~2184 bytes).
+// Z regs = 16bytes * 32 regs * 4 vq
+// P regs = 2 bytes * 16 regs * 4 vq
+// FFR reg = 2 bytes * 4 vq
+pub const MAX_VQ: u64 = 4;
 
 #[derive(Default, Debug)]
 // SIMD configuration structure
@@ -43,6 +52,9 @@ lazy_static! {
             // Get vl in bytes
             let vl_b = unsafe { get_vector_length_bytes() };
             sve_vq = ((vl_b << 3)/ QUARD_WORD) - 1;
+            if sve_vq > MAX_VQ {
+                sve_vq = MAX_VQ - 1;
+            }
             sve_en = true;
             trace!("sve_vq={:?}", sve_vq);
         }