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Merge pull request #47 from ispras/fix_dfcir_offset #6

Merge pull request #47 from ispras/fix_dfcir_offset

Merge pull request #47 from ispras/fix_dfcir_offset #6

Workflow file for this run

name: synth-sv
on:
workflow_dispatch:
push:
branches:
- master
pull_request:
branches:
- master
env:
CIRCT_VERSION: 1.72.0
CIRCT_ARCHIVE: "circt-full-shared-linux-x64.tar.gz"
DEPENDENCIES_DIR: "deps"
MLIR_TARGETS_PATH: "lib/cmake/mlir/MLIRTargets.cmake"
BUILD_DIR: "build"
UTOPIA_EXECUTABLE: "src/umain"
jobs:
synthesize-system-verilog:
strategy:
matrix:
kernel: [addconst, matrixmul2, movingsum, muxmul, polynomial2, scalar3]
config: [STUB]
## A workaround to initialize an empty config array.
exclude:
- config: STUB
include:
## addconst configs.
- kernel: addconst
config: add_int_2
## matrixmul configs.
- kernel: matrixmul2
config: add_int_2_mul_int3
## movingsum configs.
- kernel: movingsum
config: add_int_2
- kernel: movingsum
config: add_int_8
## muxmul configs.
- kernel: muxmul
config: add_int_2_mul_int3
## polynomial2 configs.
- kernel: polynomial2
config: add_int_2_mul_int3
- kernel: polynomial2
config: add_int_8_mul_int15
## scalar3 configs.
- kernel: scalar3
config: add_int_2_mul_int3
runs-on: ubuntu-latest
env:
MODULE_OUTPUT_PATH: "output.sv"
LIBRARY_OUTPUT_PATH: "lib.sv"
steps:
- name: Check out repository code
uses: actions/checkout@v4
- name: Download APT dependencies
run: |
sudo apt update
sudo apt install build-essential clang cmake g++ gcc liblpsolve55-dev lld make ninja-build libctemplate-dev verilator
- name: Download and configure CIRCT & LLVM
env:
CIRCT_SOURCE: "https://github.com/llvm/circt/releases/download/firtool-${{env.CIRCT_VERSION}}/${{env.CIRCT_ARCHIVE}}"
CIRCT_DIR: "firtool-${{env.CIRCT_VERSION}}"
run: |
mkdir "${{env.DEPENDENCIES_DIR}}"
cd "${{env.DEPENDENCIES_DIR}}"
wget "${{env.CIRCT_SOURCE}}"
tar -xvf "${{env.CIRCT_ARCHIVE}}"
sed -i 's'/\
'foreach(_target "LLVMSupport" "LLVMCore" "LLVMMC" "LLVMTarget" "LLVMAsmParser" "LLVMBinaryFormat" '\
'"LLVMBitReader" "LLVMBitWriter" "LLVMFrontendOpenMP" "LLVMTransformUtils" "LLVMTargetParser" "LLVMIRReader" '\
'"LLVMipo" "LLVMLinker" "LLVMPasses" "LLVMMCParser" "LLVMLineEditor" "LLVMTableGen" "LLVMCoroutines" "LLVMExecutionEngine" '\
'"LLVMObject" "LLVMOrcJIT" "LLVMJITLink" "LLVMAnalysis" "LLVMAggressiveInstCombine" "LLVMInstCombine" "LLVMScalarOpts" '\
'"LLVMVectorize" "LLVMX86CodeGen" "LLVMX86Desc" "LLVMX86Info" "LLVMX86AsmParser" "LLVMX86Disassembler" "CIRCTAffineToLoopSchedule" '\
'"CIRCTArcToLLVM" "CIRCTCalyxToFSM" "CIRCTCalyxToHW" "CIRCTCalyxNative" "CIRCTCombToArith" "CIRCTCombToLLVM" "CIRCTCombToSMT" '\
'"CIRCTConvertToArcs" "CIRCTDCToHW" "CIRCTExportChiselInterface" "CIRCTExportVerilog" "CIRCTFIRRTLToHW" "CIRCTFSMToSV" '\
'"CIRCTHandshakeToDC" "CIRCTHandshakeToHW" "CIRCTHWArithToHW" "CIRCTHWToLLHD" "CIRCTHWToLLVM" "CIRCTHWToBTOR2" "CIRCTHWToSMT" '\
'"CIRCTHWToSV" "CIRCTHWToSystemC" "CIRCTLLHDToLLVM" "CIRCTLoopScheduleToCalyx" "CIRCTMooreToCore" "CIRCTPipelineToHW" "CIRCTSCFToCalyx" '\
'"CIRCTSeqToSV" "CIRCTSimToSV" "CIRCTCFToHandshake" "CIRCTVerifToSMT" "CIRCTVerifToSV" "CIRCTExportFIRRTL" "CIRCTComb" '\
'"CIRCTCombTransforms" "CIRCTDebug" "CIRCTESI" "CIRCTFIRRTL" "CIRCTImportFIRFile" "CIRCTMSFT" "CIRCTMSFTTransforms" "CIRCTHW" '\
'"CIRCTLLHD" "CIRCTMoore" "CIRCTOM" "CIRCTOMEvaluator" "CIRCTSeq" "CIRCTSeqTransforms" "CIRCTSV" "CIRCTSVTransforms" "CIRCTFSM" '\
'"CIRCTFSMTransforms" "CIRCTHandshake" "CIRCTHandshakeTransforms" "CIRCTHWArith" "CIRCTVerif" "CIRCTLTL" "CIRCTEmit" "CIRCTFirtool" )'\
/\
'foreach(_target "LLVMSupport" "LLVMCore" "LLVMMC" "LLVMTarget" "LLVMAsmParser" "LLVMBinaryFormat" "LLVMBitReader" "LLVMBitWriter" '\
'"LLVMFrontendOpenMP" "LLVMTransformUtils" "LLVMTargetParser" "LLVMIRReader" "LLVMipo" "LLVMLinker" "LLVMPasses" "LLVMMCParser" '\
'"LLVMLineEditor" "LLVMTableGen" "LLVMCoroutines" "LLVMExecutionEngine" "LLVMObject" "LLVMOrcJIT" "LLVMJITLink" "LLVMAnalysis" '\
'"LLVMAggressiveInstCombine" "LLVMInstCombine" "LLVMScalarOpts" "LLVMVectorize" "LLVMX86CodeGen" "LLVMX86Desc" "LLVMX86Info" '\
'"LLVMX86AsmParser" "LLVMX86Disassembler")/' "${{env.CIRCT_DIR}}/${{env.MLIR_TARGETS_PATH}}"
cd "${{github.workspace}}"
- name: Configure Utopia HLS build
env:
CIRCT_DIR: "firtool-${{env.CIRCT_VERSION}}"
run: |
cmake -S . -B "${{env.BUILD_DIR}}" -G Ninja -DCMAKE_CXX_COMPILER=clang++ \
-DCMAKE_PREFIX_PATH="${{github.workspace}}/${{env.DEPENDENCIES_DIR}}/${{env.CIRCT_DIR}}" \
-DSRC_FILES="${{github.workspace}}/examples/${{matrix.kernel}}/${{matrix.kernel}}.cpp"
- name: Build Utopia HLS
run: |
cmake --build "${{env.BUILD_DIR}}"
- name: Run SystemVerilog modules generation
run: |
"${{env.BUILD_DIR}}/${{env.UTOPIA_EXECUTABLE}}" hls --config \
"${{github.workspace}}/examples/${{matrix.kernel}}/${{matrix.config}}.json" \
-l --out-sv "${{env.MODULE_OUTPUT_PATH}}" --out-sv-lib "${{env.LIBRARY_OUTPUT_PATH}}"
- name: Run Verilator
run: |
verilator --lint-only -Wall -Wno-DECLFILENAME "${{env.MODULE_OUTPUT_PATH}}" "${{env.LIBRARY_OUTPUT_PATH}}"