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DFCxx -> SystemVerilog pipeline parametrization #24

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Merged
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Jul 1, 2024
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DFCxx -> SystemVerilog pipeline parametrization #24

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2 changes: 1 addition & 1 deletion src/main.cpp
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Expand Up @@ -38,7 +38,7 @@ int hlsMain(HlsContext &context) {
auto kernel = start();
bool useASAP = context.options.asapScheduler;
kernel->compile(context.options.latConfig,
context.options.outFile,
{context.options.outFile},
(useASAP) ? dfcxx::Scheduler::ASAP
: dfcxx::Scheduler::Linear);
return 0;
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6 changes: 3 additions & 3 deletions src/model/dfcxx/include/dfcxx/kernel.h
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Expand Up @@ -22,6 +22,7 @@
#include "dfcxx/vars/var.h"

#include <string_view>
#include <vector>

namespace dfcxx {

Expand Down Expand Up @@ -57,9 +58,8 @@ class Kernel {

virtual std::string_view getName() = 0;

bool compile(const DFLatencyConfig &config, const Scheduler &sched);

bool compile(const DFLatencyConfig &config, const std::string &filePath,
bool compile(const DFLatencyConfig &config,
const std::vector<std::string> &outputPaths,
const Scheduler &sched);
};

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3 changes: 3 additions & 0 deletions src/model/dfcxx/include/dfcxx/typedefs.h
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Expand Up @@ -61,4 +61,7 @@ enum Scheduler {

typedef std::unordered_map<dfcxx::Ops, unsigned> DFLatencyConfig;

// Macro substitutions for indexes in a std::vector for paths.
#define SV_OUT_ID 0

#endif // DFCXX_TYPEDEFS_H
5 changes: 4 additions & 1 deletion src/model/dfcxx/includeDev/dfcxx/converter.h
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Expand Up @@ -16,14 +16,17 @@

#include <string>

typedef std::vector<llvm::raw_fd_ostream *> OutputStreams;

namespace dfcxx {

class DFCIRConverter {
private:
LatencyConfig config;
public:
explicit DFCIRConverter(const DFLatencyConfig &config);
bool convertAndPrint(mlir::ModuleOp module, llvm::raw_fd_ostream &out,
bool convertAndPrint(mlir::ModuleOp module,
OutputStreams &outputStreams,
const Scheduler &sched);
};

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4 changes: 2 additions & 2 deletions src/model/dfcxx/lib/dfcxx/converter.cpp
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Expand Up @@ -22,7 +22,7 @@ DFCIRConverter::DFCIRConverter(const DFLatencyConfig &config) {
}

bool DFCIRConverter::convertAndPrint(mlir::ModuleOp module,
llvm::raw_fd_ostream &out,
OutputStreams &outputStreams,
const Scheduler &sched) {
mlir::MLIRContext *context = module.getContext();
mlir::PassManager pm(context);
Expand All @@ -37,7 +37,7 @@ bool DFCIRConverter::convertAndPrint(mlir::ModuleOp module,
}
pm.addPass(circt::createLowerFIRRTLToHWPass());
pm.addPass(circt::createLowerSeqToSVPass());
pm.addPass(circt::createExportVerilogPass(out));
pm.addPass(circt::createExportVerilogPass(*(outputStreams[SV_OUT_ID])));
auto result = pm.run(module);
return result.succeeded();
}
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32 changes: 20 additions & 12 deletions src/model/dfcxx/lib/dfcxx/kernel.cpp
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Expand Up @@ -40,23 +40,31 @@ DFType Kernel::dfBool() {
return DFType(storage.addType(type));
}

bool Kernel::compile(const DFLatencyConfig &config, const Scheduler &sched) {
DFCIRBuilder builder(config);
auto compiled = builder.buildModule(this);
llvm::raw_fd_ostream &out = llvm::outs();
return DFCIRConverter(config).convertAndPrint(compiled, out, sched);
}

bool Kernel::compile(const DFLatencyConfig &config,
const std::string &filePath,
const std::vector<std::string> &outputPaths,
const Scheduler &sched) {
if (filePath.empty()) { return compile(config, sched); }
DFCIRBuilder builder(config);
auto compiled = builder.buildModule(this);
std::error_code ec;
llvm::raw_fd_ostream out(filePath, ec);
bool result = DFCIRConverter(config).convertAndPrint(compiled, out, sched);
out.close();
size_t count = outputPaths.size();
std::vector<llvm::raw_fd_ostream *> outputStreams(count);
// Output paths strings are converted into output streams.
for (unsigned i = 0; i < count; ++i) {
std::error_code ec;
outputStreams[i] = (!outputPaths[i].empty())
? new llvm::raw_fd_ostream(outputPaths[i], ec)
: nullptr;
}
bool result = DFCIRConverter(config).convertAndPrint(compiled,
outputStreams,
sched);
// Every created output stream has to be closed explicitly.
for (llvm::raw_fd_ostream *stream : outputStreams) {
if (stream) {
stream->close();
delete stream;
}
}
return result;
}

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4 changes: 2 additions & 2 deletions test/model/dfcxx/addconst.cpp
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Expand Up @@ -15,13 +15,13 @@ TEST(DFCxx, AddConstAddInt2Asap) {
DFLatencyConfig config = {
{dfcxx::ADD_INT, 2}
};
EXPECT_EQ(kernel.compile(config, NULLDEVICE, dfcxx::ASAP), true);
EXPECT_EQ(kernel.compile(config, {NULLDEVICE}, dfcxx::ASAP), true);
}

TEST(DFCxx, AddConstAddInt2Linear) {
AddConst kernel;
DFLatencyConfig config = {
{dfcxx::ADD_INT, 2}
};
EXPECT_EQ(kernel.compile(config, NULLDEVICE, dfcxx::Linear), true);
EXPECT_EQ(kernel.compile(config, {NULLDEVICE}, dfcxx::Linear), true);
}
4 changes: 2 additions & 2 deletions test/model/dfcxx/idct.cpp
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Expand Up @@ -17,7 +17,7 @@ TEST(DFCxx, IdctAsap) {
{dfcxx::MUL_INT, 3},
{dfcxx::SUB_INT, 1}
};
EXPECT_EQ(kernel.compile(config, NULLDEVICE, dfcxx::ASAP), true);
EXPECT_EQ(kernel.compile(config, {NULLDEVICE}, dfcxx::ASAP), true);
}

// Issue #7 (https://github.com/ispras/utopia-hls/issues/7).
Expand All @@ -29,5 +29,5 @@ TEST(DFCxx, IdctAsap) {
// {dfcxx::MUL_INT, 3},
// {dfcxx::SUB_INT, 1}
// };
// EXPECT_EQ(kernel.compile(config, NULLDEVICE, dfcxx::Linear), true);
// EXPECT_EQ(kernel.compile(config, {NULLDEVICE}, dfcxx::Linear), true);
// }
4 changes: 2 additions & 2 deletions test/model/dfcxx/matrixmul2.cpp
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Expand Up @@ -16,7 +16,7 @@ TEST(DFCxx, MatrixMul2AddInt2MulInt3Asap) {
{dfcxx::ADD_INT, 2},
{dfcxx::MUL_INT, 3},
};
EXPECT_EQ(kernel.compile(config, NULLDEVICE, dfcxx::ASAP), true);
EXPECT_EQ(kernel.compile(config, {NULLDEVICE}, dfcxx::ASAP), true);
}

TEST(DFCxx, MatrixMul2AddInt2MulInt3Linear) {
Expand All @@ -25,5 +25,5 @@ TEST(DFCxx, MatrixMul2AddInt2MulInt3Linear) {
{dfcxx::ADD_INT, 2},
{dfcxx::MUL_INT, 2},
};
EXPECT_EQ(kernel.compile(config, NULLDEVICE, dfcxx::Linear), true);
EXPECT_EQ(kernel.compile(config, {NULLDEVICE}, dfcxx::Linear), true);
}
8 changes: 4 additions & 4 deletions test/model/dfcxx/movingsum.cpp
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Expand Up @@ -15,29 +15,29 @@ TEST(DFCxx, MovingSumAddInt2Asap) {
DFLatencyConfig config = {
{dfcxx::ADD_INT, 2}
};
EXPECT_EQ(kernel.compile(config, NULLDEVICE, dfcxx::ASAP), true);
EXPECT_EQ(kernel.compile(config, {NULLDEVICE}, dfcxx::ASAP), true);
}

TEST(DFCxx, MovingSumAddInt2Linear) {
MovingSum kernel;
DFLatencyConfig config = {
{dfcxx::ADD_INT, 2}
};
EXPECT_EQ(kernel.compile(config, NULLDEVICE, dfcxx::Linear), true);
EXPECT_EQ(kernel.compile(config, {NULLDEVICE}, dfcxx::Linear), true);
}

TEST(DFCxx, MovingSumAddInt8Asap) {
MovingSum kernel;
DFLatencyConfig config = {
{dfcxx::ADD_INT, 8}
};
EXPECT_EQ(kernel.compile(config, NULLDEVICE, dfcxx::ASAP), true);
EXPECT_EQ(kernel.compile(config, {NULLDEVICE}, dfcxx::ASAP), true);
}

TEST(DFCxx, MovingSumAddInt8Linear) {
MovingSum kernel;
DFLatencyConfig config = {
{dfcxx::ADD_INT, 8}
};
EXPECT_EQ(kernel.compile(config, NULLDEVICE, dfcxx::Linear), true);
EXPECT_EQ(kernel.compile(config, {NULLDEVICE}, dfcxx::Linear), true);
}
4 changes: 2 additions & 2 deletions test/model/dfcxx/muxmul.cpp
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Expand Up @@ -16,7 +16,7 @@ TEST(DFCxx, MuxMulAddInt2MulInt3Asap) {
{dfcxx::ADD_INT, 2},
{dfcxx::MUL_INT, 3}
};
EXPECT_EQ(kernel.compile(config, NULLDEVICE, dfcxx::ASAP), true);
EXPECT_EQ(kernel.compile(config, {NULLDEVICE}, dfcxx::ASAP), true);
}

TEST(DFCxx, MuxMulAddInt2MulInt3Linear) {
Expand All @@ -25,5 +25,5 @@ TEST(DFCxx, MuxMulAddInt2MulInt3Linear) {
{dfcxx::ADD_INT, 2},
{dfcxx::MUL_INT, 3}
};
EXPECT_EQ(kernel.compile(config, NULLDEVICE, dfcxx::Linear), true);
EXPECT_EQ(kernel.compile(config, {NULLDEVICE}, dfcxx::Linear), true);
}
8 changes: 4 additions & 4 deletions test/model/dfcxx/polynomial2.cpp
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Expand Up @@ -16,7 +16,7 @@ TEST(DFCxx, Polynomial2AddInt2MulInt3Asap) {
{dfcxx::ADD_INT, 2},
{dfcxx::MUL_INT, 3}
};
EXPECT_EQ(kernel.compile(config, NULLDEVICE, dfcxx::ASAP), true);
EXPECT_EQ(kernel.compile(config, {NULLDEVICE}, dfcxx::ASAP), true);
}

TEST(DFCxx, Polynomial2AddInt2MulInt3Linear) {
Expand All @@ -25,7 +25,7 @@ TEST(DFCxx, Polynomial2AddInt2MulInt3Linear) {
{dfcxx::ADD_INT, 2},
{dfcxx::MUL_INT, 3}
};
EXPECT_EQ(kernel.compile(config, NULLDEVICE, dfcxx::Linear), true);
EXPECT_EQ(kernel.compile(config, {NULLDEVICE}, dfcxx::Linear), true);
}

TEST(DFCxx, Polynomial2AddInt8MulInt15Asap) {
Expand All @@ -34,7 +34,7 @@ TEST(DFCxx, Polynomial2AddInt8MulInt15Asap) {
{dfcxx::ADD_INT, 8},
{dfcxx::MUL_INT, 15}
};
EXPECT_EQ(kernel.compile(config, NULLDEVICE, dfcxx::ASAP), true);
EXPECT_EQ(kernel.compile(config, {NULLDEVICE}, dfcxx::ASAP), true);
}

TEST(DFCxx, Polynomial2AddInt8MulInt15Linear) {
Expand All @@ -43,5 +43,5 @@ TEST(DFCxx, Polynomial2AddInt8MulInt15Linear) {
{dfcxx::ADD_INT, 8},
{dfcxx::MUL_INT, 15}
};
EXPECT_EQ(kernel.compile(config, NULLDEVICE, dfcxx::Linear), true);
EXPECT_EQ(kernel.compile(config, {NULLDEVICE}, dfcxx::Linear), true);
}
4 changes: 2 additions & 2 deletions test/model/dfcxx/scalar3.cpp
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Expand Up @@ -16,7 +16,7 @@ TEST(DFCxx, Scalar3AddInt2MulInt3Asap) {
{dfcxx::ADD_INT, 2},
{dfcxx::MUL_INT, 3}
};
EXPECT_EQ(kernel.compile(config, NULLDEVICE, dfcxx::ASAP), true);
EXPECT_EQ(kernel.compile(config, {NULLDEVICE}, dfcxx::ASAP), true);
}

TEST(DFCxx, Scalar3AddInt2MulInt3Linear) {
Expand All @@ -25,5 +25,5 @@ TEST(DFCxx, Scalar3AddInt2MulInt3Linear) {
{dfcxx::ADD_INT, 2},
{dfcxx::MUL_INT, 3}
};
EXPECT_EQ(kernel.compile(config, NULLDEVICE, dfcxx::Linear), true);
EXPECT_EQ(kernel.compile(config, {NULLDEVICE}, dfcxx::Linear), true);
}