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from .bus import * | ||
from .event import * | ||
from .reg import * | ||
from . import field |
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from .reg import GenericField | ||
from amaranth import * | ||
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from .reg import Field | ||
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__all__ = ["R", "W", "RW", "RW1C", "RW1S"] | ||
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# Capabilities | ||
class R(Field): | ||
def __init__(self, shape): | ||
super().__init__(shape, access="r") | ||
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def elaborate(self, platform): | ||
m = Module() | ||
m.d.comb += self.port.r_data.eq(self.data) | ||
return m | ||
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class W(Field): | ||
def __init__(self, shape): | ||
super().__init__(shape, access="w") | ||
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def elaborate(self, platform): | ||
m = Module() | ||
m.d.comb += self.data.eq(self.port.w_data) | ||
return m | ||
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class RW(Field): | ||
def __init__(self, shape, *, reset=0): | ||
super().__init__(shape, access="rw") | ||
self._storage = Signal(shape, reset=reset) | ||
self._reset = reset | ||
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@property | ||
def reset(self): | ||
return self._reset | ||
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def elaborate(self, platform): | ||
m = Module() | ||
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with m.If(self.port.w_stb): | ||
m.d.sync += self._storage.eq(self.port.w_data) | ||
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class _IntrRead: | ||
@staticmethod | ||
def intr_read(storage): | ||
return storage | ||
m.d.comb += [ | ||
self.port.r_data.eq(self._storage), | ||
self.data.eq(self._storage), | ||
] | ||
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return m | ||
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class _IntrWrite: | ||
@staticmethod | ||
def intr_write(storage, w_data): | ||
return w_data | ||
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class RW1C(Field): | ||
def __init__(self, shape, *, reset=0): | ||
super().__init__(shape, access="rw") | ||
self.set = Signal(shape) | ||
self._storage = Signal(shape, reset=reset) | ||
self._reset = reset | ||
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class _IntrSet: | ||
@staticmethod | ||
def intr_write(storage, w_data): | ||
return storage | w_data | ||
@property | ||
def reset(self): | ||
return self._reset | ||
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def elaborate(self, platform): | ||
m = Module() | ||
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class _IntrClear: | ||
@staticmethod | ||
def intr_write(storage, w_data): | ||
return storage & ~w_data | ||
for i, storage_bit in enumerate(self._storage): | ||
with m.If(self.port.w_stb & self.port.w_data[i]): | ||
m.d.sync += storage_bit.eq(0) | ||
with m.If(self.set[i]): | ||
m.d.sync += storage_bit.eq(1) | ||
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m.d.comb += [ | ||
self.port.r_data.eq(self._storage), | ||
self.data.eq(self._storage), | ||
] | ||
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class _UserWrite: | ||
@staticmethod | ||
def user_write(storage, w_data): | ||
return w_data | ||
return m | ||
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class _UserSet: | ||
@staticmethod | ||
def user_write(storage, w_data): | ||
return storage | w_data | ||
class RW1S(Field): | ||
def __init__(self, shape, *, reset=0): | ||
super().__init__(shape, access="rw") | ||
self.clear = Signal(shape) | ||
self._storage = Signal(shape, reset=reset) | ||
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@property | ||
def reset(self): | ||
return self._reset | ||
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class _UserClear: | ||
@staticmethod | ||
def user_write(storage, w_data): | ||
return storage & ~w_data | ||
def elaborate(self, platform): | ||
m = Module() | ||
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for i, storage_bit in enumerate(self._storage): | ||
with m.If(self.clear[i]): | ||
m.d.sync += storage_bit.eq(0) | ||
with m.If(self.port.w_stb & self.port.w_data[i]): | ||
m.d.sync += storage_bit.eq(1) | ||
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# Field types | ||
m.d.comb += [ | ||
self.port.r_data.eq(self._storage), | ||
self.data.eq(self._storage), | ||
] | ||
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class R (_IntrRead, _UserWrite, GenericField): intr_write = None | ||
class W ( _IntrWrite, GenericField): intr_read = None; user_write = None | ||
class RW (_IntrRead, _IntrWrite, GenericField): user_write = None | ||
class RW1C(_IntrRead, _IntrClear, _UserSet, GenericField): pass | ||
class RW1S(_IntrRead, _IntrSet, _UserClear, GenericField): pass | ||
return m |
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