Merge pull request eirikpre#219 from joecrop/rel-0-13-8

Added syntax highlighting support for sdc/xdc files

CHANGELOG.md

@@ -10,6 +10,10 @@ More details can be found on the [Releases](https://github.com/eirikpre/VSCode-S
 - 💡 Back-end Language Server for Systemverilog
 - 💡 Complete syntax highlighting
 
+### [0.13.9]
+
+- Added basic syntax highlighting support for sdc/xdc files inspired by [https://github.com/mshr-h/vscode-verilog-hdl-support](vscode-verilog-hdl-support) by `joecrop`
+
 ### [0.13.8]
 
 - Corrected icons for light themes by `joecrop`

configs/scd.json

@@ -0,0 +1,24 @@
+{
+  "comments": {
+    "lineComment": "#"
+  },
+  "brackets": [
+    ["{", "}"],
+    ["[", "]"],
+    ["(", ")"]
+  ],
+  "autoClosingPairs": [
+    ["{", "}"],
+    ["[", "]"],
+    ["(", ")"],
+    ["\"", "\""],
+    ["'", "'"]
+  ],
+  "surroundingPairs": [
+    ["{", "}"],
+    ["[", "]"],
+    ["(", ")"],
+    ["\"", "\""],
+    ["'", "'"]
+  ]
+}

configs/verilogFileList.json

@@ -1,5 +1,17 @@
 {
 	"comments": {
 		"lineComment": ["//", "#"]
-  }
+  },
+	"brackets": [
+    ["{", "}"],
+    ["(", ")"]
+  ],
+  "autoClosingPairs": [
+    ["{", "}"],
+    ["(", ")"]
+  ],
+  "surroundingPairs": [
+    ["{", "}"],
+    ["(", ")"]
+  ]
 }

package.json

@@ -2,7 +2,7 @@
     "name": "systemverilog",
     "displayName": "SystemVerilog - Language Support",
     "description": "Language support for Verilog and SystemVerilog.",
-    "version": "0.13.8",
+    "version": "0.13.9",
     "publisher": "eirikpre",
     "author": {
         "name": "Eirik Prestegårdshus",
@@ -155,6 +155,34 @@
                     "light": "./resources/f_light.svg",
                     "dark": "./resources/f_dark.svg"
                 }
+            },
+            {
+                "id": "sdc",
+                "aliases": [
+                    "Synopsys Design Constraints"
+                ],
+                "extensions": [
+                    ".sdc"
+                ],
+                "configuration": "./configs/sdc.json",
+                "icon": {
+                    "light": "./resources/sdc_light.svg",
+                    "dark": "./resources/sdc_dark.svg"
+                }
+            },
+            {
+                "id": "xdc",
+                "aliases": [
+                    "Xilinx Design Constraints"
+                ],
+                "extensions": [
+                    ".xdc"
+                ],
+                "configuration": "./configs/sdc.json",
+                "icon": {
+                    "light": "./resources/sdc_light.svg",
+                    "dark": "./resources/sdc_dark.svg"
+                }
             }
         ],
         "snippets": [
@@ -221,6 +249,16 @@
                 "language": "verilog-filelist",
                 "scopeName": "source.verilog-filelist",
                 "path": "./syntaxes/verilog-filelist.json"
+            },
+            {
+                "language": "sdc",
+                "scopeName": "source.sdc",
+                "path": "./syntaxes/sdc.json"
+            },
+            {
+                "language": "xdc",
+                "scopeName": "source.sdc",
+                "path": "./syntaxes/sdc.json"
             }
         ],
         "configuration": [