kiriware / Logisim-16-bit-RISC-Processor Public

Notifications You must be signed in to change notification settings
Fork 0
Star 2

Logisim implementation of a 16-bit single cycle and pipelined RISC processor designed from an instruction set.

2 stars 0 forks Branches Tags Activity

Notifications

Name		Name	Last commit message	Last commit date
Latest commit History 23 Commits
images		images
pipelined		pipelined
single-cycle		single-cycle
README.md		README.md

Repository files navigation

Logisim-16-bit-RISC-Processor

Logisim implementation of a 16-bit single cycle and pipelined RISC processor designed from an instruction set.

Instruction Set:

About

Logisim implementation of a 16-bit single cycle and pipelined RISC processor designed from an instruction set.

processor-architecture logisim logisim-cpu logisim-alu

Report repository

Releases

No releases published