Try skip compile pattern

leonardt · Nov 21, 2023 · 1030dd9 · 1030dd9
1 parent 1dd2098
commit 1030dd9
Showing 1 changed file with 5 additions and 5 deletions.
diff --git a/tests/test_property.py b/tests/test_property.py
@@ -915,8 +915,8 @@ class Main(m.Circuit):
     tester.circuit.I = 0
     tester.compile_and_run("system-verilog", simulator="ncsim",
                            magma_output="mlir-verilog", flags=["-sv"],
-                           magma_opts={"sv": True}, disp_type="realtime",
-                           coverage=True)
+                           skip_compile=True, magma_opts={"sv": True},
+                           disp_type="realtime", coverage=True)
 
     out, _ = capsys.readouterr()
     assert """\
@@ -932,7 +932,8 @@ class Main(m.Circuit):
     tester.advance_cycle()
     tester.compile_and_run("system-verilog", simulator="ncsim",
                            flags=["-sv"], magma_opts={"sv": True},
-                           disp_type="realtime", coverage=True)
+                           skip_compile=True, disp_type="realtime",
+                           coverage=True)
 
     out, _ = capsys.readouterr()
     assert """\
@@ -949,8 +950,7 @@ class Main(m.Circuit):
                            simulator="ncsim",
                            magma_output="mlir-verilog",
                            flags=["-sv"],
-                           magma_opts={"sv": True,
-                                       "disable_initial_blocks": True},
+                           skip_compile=True,
                            disp_type="realtime",
                            coverage=True)