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Update opts
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leonardt committed Nov 21, 2023
1 parent d482c64 commit 8cd51cd
Showing 1 changed file with 10 additions and 7 deletions.
17 changes: 10 additions & 7 deletions tests/test_property.py
Original file line number Diff line number Diff line change
Expand Up @@ -894,8 +894,9 @@ class Main(m.Circuit):
tester.circuit.I = 1
tester.advance_cycle()
tester.compile_and_run("system-verilog", simulator="ncsim",
flags=["-sv"], magma_opts={"inline": True},
disp_type="realtime", coverage=True)
magma_output="mlir-verilog", flags=["-sv"],
magma_opts={"sv": True}, disp_type="realtime",
coverage=True)

out, _ = capsys.readouterr()
# not covered
Expand All @@ -909,8 +910,9 @@ class Main(m.Circuit):
tester.advance_cycle()
tester.circuit.I = 0
tester.compile_and_run("system-verilog", simulator="ncsim",
flags=["-sv"], magma_opts={"inline": True},
disp_type="realtime", coverage=True)
magma_output="mlir-verilog", flags=["-sv"],
magma_opts={"sv": True}, disp_type="realtime",
coverage=True)

out, _ = capsys.readouterr()
# covered
Expand All @@ -925,7 +927,7 @@ class Main(m.Circuit):
tester.circuit.I = 1
tester.advance_cycle()
tester.compile_and_run("system-verilog", simulator="ncsim",
flags=["-sv"], magma_opts={"inline": True},
flags=["-sv"], magma_opts={"sv": True},
disp_type="realtime", coverage=True)

out, _ = capsys.readouterr()
Expand All @@ -940,8 +942,9 @@ class Main(m.Circuit):
tester.advance_cycle()
tester.circuit.I = 0
tester.compile_and_run("system-verilog", simulator="ncsim",
flags=["-sv"], magma_opts={"inline": True},
disp_type="realtime", coverage=True)
magma_output="mlir-verilog", flags=["-sv"],
magma_opts={"sv": True}, disp_type="realtime",
coverage=True)

out, _ = capsys.readouterr()
# covered
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