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Update README.md
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leonardt authored Sep 26, 2020
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Expand Up @@ -286,12 +286,12 @@ For example:
```python
tester.compile_and_run(target="system-verilog", simulator="vcs",
waveform_type="fsdb", dump_waveforms=True,
fsdb_dumpvars_args='0, "top"')
fsdb_dumpvars_args='0, "dut"')
```

will produce:
```verilog
$fsdbDumpvars(0, "top");
$fsdbDumpvars(0, "dut");
```

inside the generated test bench.
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