Add support for IPQ8064 SoC #22
Conversation
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@lumag I tried to implement the suggestion of using additional leaf... Hope it's not a problem for the funny implementation of If required I can merge gcc and hs but I think it may be confusing since there are also test bus regs there... Chance for apq8064 to recycle this implementation if it does have test bus stuff defined. Indeed with the current implementation the vector table is much cleaner |
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My opinion is that it is much better now. I'd like to take a look at reworking the primary/leaf muxes, but this will take some time (and ipq8064 serves a perfect example here). apq8064 is even more complex, it has separate mm muxes. |
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@Ansuel we have landed support for chained muxes. Could you please rebased your patches on top of the current master branch? We can work on merging it afterwards. |
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Sure! |
Unsigned long have a different size in 32 bit system and this cause the malfunction of debugcc returning wrong frequency. Use 64bit unsigned int to correctly support 32 bit system and provide correct frequency. Signed-off-by: Christian Marangi <[email protected]>
Some xo require special value to set it to /4 divisor. Introduce xo_div4_val to handle this special implementation. Signed-off-by: Christian Marangi <[email protected]>
Some device have a different rate for the xo debug oscillator. Add support for defining custom xo rate in the primary debug mux. Signed-off-by: Christian Marangi <[email protected]>
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@lumag rebased and tested. Values match the old implementation and very nice code cleanup with the new parent way! |
Add convenient macro GENMASK to calculate masks from bits similar to how it's implemented in kernel linux tools. This is useful to better describe some specific define instead of using comments and raw HEX values. Signed-off-by: Christian Marangi <[email protected]>
Add support for IPQ8064 SoC. All the debug vector are taken from old pre-dt linux-msm source. To correctly setup the debug oscillator, it's required to operate on 2 different clk, the CXO oscillator and the PDM clock. Then we operate ton the CLK_TEST reg and we setup the required vector. With the use of define we abstract everything for the high speed and the low speed clocks. The CXO oscillator runs at 25Mhz and a different xo_rate is required than the current default one. We can also test the 2 CPU speed and the current L2 speed using the APCS CLK_DIAG reg. To test this we need to setup a special test vector in CLK_TEST and then operate on the APCS reg. For these special clock a different fixed_div is needed to be set. There is currently a bug (probably a hw bug) where the CPU clock of the 2 core is half broken, the correct clock is reported but only for one of the core, the other core will always report a wrong clock. Operating on the CPU mux makes the CLK_DIAG report the correct freq on one of the 2 core from the test vector. Also the L2 clock seems to be half broken with high speed freq. (still has to be confirmed and maybe it's the L2 HFPLL wrongly configured for some reason and on high frequency > 1GHz reports not precise frequency) Note that we currently use a fixed_div of 8 for these special clock. This should be used only for ipq8064 v3 SoC but it was never found an ipq8064 v1 SoC, where 2 should be used as fixed_div. Signed-off-by: Christian Marangi <[email protected]>
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@lumag sorry for changing this again... but since it's 99% ready I also decided to add the GENMASK commit and switch to it. (took the define from linux kernel tools) |
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@Ansuel no problem. I agree with you, |
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... and merged. Thanks a lot! |
Add support for IPQ8064 SoC. All the debug vector are taken from old
pre-dt linux-msm source.
To correctly setup the debug oscillator, it's required to operate on 2
different clk, the CXO oscillator and the PDM clock. Then we operate ton
the CLK_TEST reg and we setup the required vector. With the use of
define we abstract everything for the high speed and the low speed
clocks.
The CXO oscillator runs at 25Mhz and a different xo_rate is required
than the current default one.
We can also test the 2 CPU speed and the current L2 speed using the APCS
CLK_DIAG reg. To test this we need to setup a special test vector in
CLK_TEST and then operate on the APCS reg.
For these special clock a different fixed_div is needed to be set and a
different sample_ticks is required to correctly calculate the reported
freq.
There is currently a bug (probably a hw bug) where the CPU clock of the
2 core is half broken, the correct clock is reported but only for one of
the core, the other core will always report a wrong clock. Operating on
the CPU mux makes the CLK_DIAG report the correct freq on one of the 2
core from the test vector.
Also the L2 clock seems to be half broken with high speed freq. (still
has to be confirmed and maybe it's the L2 HFPLL wrongly configured for
some reason and on high frequency > 1GHz reports not precise frequency)
Note that we currently use a fixed_div of 8 for these special clock.
This should be used only for ipq8064 v3 SoC but it was never found an
ipq8064 v1 SoC, where 2 should be used as fixed_div.
Signed-off-by: Christian Marangi [email protected]
Additional patch were required to the generic code to support this legacy SoC.
The testing vector I found are from an old linux-msm source before it was dropped.
The implementation is 1:1 to the apq8064 so I expect more vector can be supported but I prefer to stick to the original definition.