Update chips4makers cells #95
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Created draft pull request as I was not able yet to test changes locally myself, working on that now. |
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@jpc-lip6 Also did pull request from own fork as I don't have push rights to lip6/alliance-check-toolkit repo directly. |
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* Remove ExampleSRAMs files as it has been disabled in upstream project * Remove vbe views, they were there in previous version but were not from the Chips4Makers export code. They not seen as needed for the current flow. * Update StdCellLib standard cell library to latest version including area optimization * Added StdCellLambaLib standard cell library * The pin direction is now handled inside the generated standard cell library and does not need to be done in _fix.py file anymore. * Remove _hitas.spi versions of the spice models. Provided model files should be usable as is in HiTAS/Yagle when setting `avt_config simToolModel hspice`
* Reduce area
* Update blif file; used code
#!/bin/env python3
conv_text = (
("o2_x2", "or2_x1", None, None),
("o3_x2", "or3_x1", None, None),
("o4_x2", "or4_x1", None, None),
("a2_x2", "and2_x1", None, None),
("a3_x2", "and3_x1", None, None),
("a4_x2", "and4_x1", None, None),
("mx2_x2", "mux2_x1", None, None),
("nxr2_x1", "nexor2_x0", None, None), # Needs to be before next one
("xr2_x1", "xor2_x0", None, None),
("sff1_x4", "dff_x1", "ck=", "clk="),
("sff1r_x4", "dffnr_x1", "ck=", "clk="),
("ao22_x2", "and21nor_x1", "q=", "nq="),
("oa22_x2", "or21nand_x1", "q=", "nq="),
)
with open("non_generated/user_project_core_lambdasoc.blif", "r") as fin:
with open("user_project_core_lambdasoc.blif", "w") as fout:
for line in fin:
for s, r, s2, r2 in conv_text:
if s in line:
line = line.replace(s, r)
if s2 is not None:
line = line.replace(s2, r2)
fout.write(line)
TODO: PnR still fails.
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avt_config simToolModel hspice