[ExportVerilog] Add option to limit identifier length

[teqdruid]

Some frontends emit reaaaaaaaally long identifiers. Not a problem for CIRCT but some EDA tools (cough cough Quartus) choke on those long identifiers. We should add an option to limit the number of characters in identifiers we emit to verilog to N.

[teqdruid]

@uenoku is this just a matter of adding a lowering option which affects the name sanitizer? I haven't played in the ExportVerilog stuff for years now.

[uenoku]

Yes, I think this commit does something similar. Basically you can add a length option, pass it to sv::legalizeName, and rename long identifiers to something else.

The SV specs say 1024 characters is the limit (though it also says 'up to,' so it is generally tool-dependent). If Quartus supports 1024 characters, then I think it's reasonable to make this the default behavior without an additional option.

[teqdruid]

Thanks for the pointer!

The SV specs say 1024 characters is the limit

I did not know the SV spec specified 1024 to be the limit! In that case I agree -- no lowering option necessary as of now.

[seldridge]

An issue tracking the known limits is here: #808