Skip to content

Pull requests: llvm/circt

New pull request New
172 Open 6,590 Closed
172 Open 6,590 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Reviews
Filter by reviews
No reviews Review required Approved review Changes requested
Assignee
Filter by who’s assigned
Assigned to nobody Loading
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Pull requests list

[LLHD] Allow multiple layers of inlined functions to be followed by the same op
#9119 opened Oct 20, 2025 by georgerennie Loading…
1
[Synth][LowerVariadic] Fix a dialect dependency
#9118 opened Oct 20, 2025 by uenoku Loading…
1
[ImportVerilog] Add support for string materialization ImportVerilog
#9112 opened Oct 19, 2025 by Scheremo Loading…
3
[FIRRTL] Support domain.define in LoweDomains
#9108 opened Oct 18, 2025 by seldridge Loading…
[FIRRTL] Domain inference
#9106 opened Oct 17, 2025 by rwy7 • Draft
[Conversion] Add comprehensive CombToLLVM conversion pass with func.func-only scope
#9105 opened Oct 17, 2025 by prithayan • Draft
Deduplicate mulitple moore.procedure ops that with identical wait_eve…
#9101 opened Oct 16, 2025 by SimonEbner Loading…
[ESI] Add serde support for wide integers
#9091 opened Oct 14, 2025 by mortbopet Loading…
1
[FIRRTL] Add domain info verification to instance ops
#9074 opened Oct 9, 2025 by rwy7 Loading…
1
No custom printer for CompReg - leading to loss of quotation marks Resolves #8833 bug Something isn't working Seq Involving the `seq` dialect
#9049 opened Oct 4, 2025 by KaiS987 Loading…
1
1
Add an attribute to hw.module.extern referencing emit.file ops that implement them
#9047 opened Oct 2, 2025 by tmckay-sifive Loading…
5
fix: corner cases in aggregate generation
#9036 opened Sep 30, 2025 by tianrui-wei Loading…
6
[Synth ] feat : Fold Majority Graph
#9033 opened Sep 27, 2025 by markram1729 • Draft
21
[LTL] Add explict clocked operations and types
#9026 opened Sep 26, 2025 by Clo91eaf • Draft
8
fix: use NLA to preserve externalized memory from being dropped
#9012 opened Sep 24, 2025 by tianrui-wei Loading…
1
5
[DoNotMerge] Add signal trace capability to arcilator Arc Involving the `arc` dialect
#8986 opened Sep 18, 2025 by fzi-hielscher • Draft
1
[ESI] Unpack dictionary arguments for CallbackPort callbacks
#8916 opened Sep 2, 2025 by mortbopet Loading…
1
[ESI] Throw exceptions on invalid deserialization
#8914 opened Sep 2, 2025 by mortbopet Loading…
3
[ESI] Don't swallow exception in callback port wrapper
#8913 opened Sep 2, 2025 by mortbopet Loading…
3
[Verif] fix : Verif Clock I1 to !seq.clock
#8907 opened Aug 30, 2025 by markram1729 • Draft
[FIRRTL] Add InferDomains pass
#8877 opened Aug 20, 2025 by seldridge • Draft
6
[LLHD] Remove redundant destination operands from wait operation LLHD
#8870 opened Aug 18, 2025 by mvpant • Draft
19
[circt-opt] Add pass --convert-core-to-fsm
#8852 opened Aug 14, 2025 by AtticusKuhn Loading…
20
[SV] Remove extract-test-code
#8846 opened Aug 12, 2025 by rwy7 Loading…
6
Add check for casting bundle with elements in different directions
#8750 opened Jul 21, 2025 by unlsycn Loading…
1
ProTip! Adding no:label will show everything without a label.