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Pull requests: llvm/circt

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Pull requests list

[Synth] Improve the truth table expansion of > 6 inputs
#10420 opened May 9, 2026 by okekayode Contributor Loading…
5
[ESI][Runtime] Add integration tests for ordering issues ESI
#10418 opened May 8, 2026 by teqdruid Contributor Loading…
5
[LTL] Add ClockedDelayOp description
#10415 opened May 8, 2026 by Clo91eaf Contributor Loading…
8
[FIRRTL] Add mux2cell/mux4cell canonicalization patterns
#10414 opened May 8, 2026 by anaumchev Loading…
1
[Arc] Remove optional enable operands of MemoryWriteOp and StateWriteOp Arc Involving the `arc` dialect
#10411 opened May 7, 2026 by fzi-hielscher Contributor Loading…
1
1
[debug][firrtl] Carry Chisel source-level types through the pipeline
#10410 opened May 7, 2026 by fkhaidari Loading…
[HW] HWVectorization Part 4: Partial Vectorization (Chunking)
#10399 opened May 6, 2026 by mafeguimaraes Contributor Loading…
[ImportVerilog] Resolve modport member accesses through interface ports
#10398 opened May 6, 2026 by micprog Loading…
[arc][LowerToLLVM] Handle i0 types more rigorously
#10393 opened May 6, 2026 by jmolloy Contributor Loading…
4
[LTL] Make PastOp clock operand mandatory
#10392 opened May 6, 2026 by TaoBi22 Contributor Loading…
3
[Synth] Add attribute for linear delay model and pass to approximate them from NLDM attr
#10385 opened May 5, 2026 by okekayode Contributor Loading…
16
[CI] Enable macos wheel building
#10371 opened May 1, 2026 by jumerckx Loading…
11
[Support] Add parallel instance graph visitors
#10353 opened Apr 29, 2026 by seldridge Member • Draft
4
[ImportVerilog] Support use-before-declare across module bodies
#10350 opened Apr 28, 2026 by AmurG Contributor Loading…
1
[FIRRTL] LowerLayers: Inline enabled layers FIRRTL Involving the `firrtl` dialect
#10348 opened Apr 28, 2026 by rwy7 Contributor Loading…
4
[Sim][MooreToCore] Lowering moore.fmt.string op to the new sim.fmt.string
#10346 opened Apr 28, 2026 by sunhailong2001 Contributor Loading…
5
[ImportVerilog] HierarchicalNames should skip reprocessing identical module instances
#10341 opened Apr 28, 2026 by rocallahan Contributor • Draft
3
fix: update flattenIndices to generate correct indices for a flattened memref
#10327 opened Apr 25, 2026 by Abhilekhgautam Loading…
1
6
[Support] Add SparseOpSCC utility
#10305 opened Apr 23, 2026 by fzi-hielscher Contributor Loading…
17
[FIRRTL] Eliminate Implicit Truncation
#10294 opened Apr 21, 2026 by darthscsi Contributor Loading…
17
[OM] Introduce explicit evaluator state and op patterns
#10265 opened Apr 18, 2026 by uenoku Member • Draft
1
14
[LowerToHW] Avoid "assert/assume/cover" string comparison, refactor label creation, NFC
#10251 opened Apr 17, 2026 by uenoku Member Loading…
Plumb dbg.variable anchors into SMT symbol names
#10237 opened Apr 16, 2026 by 5iri Contributor Loading…
6
ImportVerilog: fix signedness propagation in ConversionExpression lowering
#10235 opened Apr 16, 2026 by kaituo-crypto Loading…
7
[Synth] Make FunctionalReduction runnable on any op
#10230 opened Apr 15, 2026 by SmitVaishnav Contributor Loading…
3
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