The X86ISD::VPMADD52L/VPMADD52H nodes truncates each element of operands 0 and 1 from 64-bits to 52-bits, unsigned multiplies them together and then extracts the lo/hi 52-bit result, zero-extends back to 64-bits and adds to the corresponding 64-bits element of operand 3.

computeKnownBitsForTargetNode needs to correctly handle X86ISD::VPMADD52L/VPMADD52H nodes with suitable test coverage

NOTE that the operand order appears to be different to the instruction encoding - so this might need to be checked on actual hardware (Cannonlake/IceLake/Znver4 probably).

Pulled out of #153787