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Pull requests list

[mlir][ptr] Extend ptr_add operation to support shaped operands mlir:llvm mlir
#156374 opened Sep 1, 2025 by fabianmcg Loading…
6
[HLSL][DirectX] Add support for rootsig as a target environment
#156373 opened Sep 1, 2025 by inbelic Loading…
1
[DirectX] Add only-section to llvm-objcopy for DXContainer backend:DirectX llvm:binary-utilities
#156372 opened Sep 1, 2025 by inbelic Loading…
1
2
[LLDB] Complete constant array member types in class members lldb
#156370 opened Sep 1, 2025 by Nerixyz Loading…
1
[Headers][X86] Allow SSE2/AVX2/AVX512F/AVX512BW/AVX512DQ integer multiply intrinsics to be used in constexpr backend:X86 clang:headers Headers provided by Clang, e.g. for intrinsics clang Clang issues not falling into any other category
#156369 opened Sep 1, 2025 by eulerkochy • Draft
1
2
[mlir][ptr] Add gather, masked_load, masked_store, and scatter ops mlir:llvm mlir
#156368 opened Sep 1, 2025 by fabianmcg Loading…
6
improve debug messages in dependence analysis llvm:analysis Includes value tracking, cost tables and constant folding
#156367 opened Sep 1, 2025 by sebpop Loading…
1
[llvm-reduce] Treat CallBrInst as Branch tools:llvm-reduce
#156366 opened Sep 1, 2025 by XChy Loading…
Add proper handling of \note, \warning and \retval command + change render kind of command arguments.
#156365 opened Sep 1, 2025 by tcottin • Draft
[AArch64] Remove post-decoding instruction mutations
#156364 opened Sep 1, 2025 by s-barannikov • Draft
2
[AArch64] Provide a custom decoder for LDR_ZA/STR_ZA
#156363 opened Sep 1, 2025 by s-barannikov • Draft
1
[AArch64] Correctly disassemble TSB instruction
#156362 opened Sep 1, 2025 by s-barannikov • Draft
1
[AVR] Remove workarounds for instructions using Z register
#156361 opened Sep 1, 2025 by s-barannikov • Draft
1
[RISCV] Remove post-decoding instruction adjustments
#156360 opened Sep 1, 2025 by s-barannikov • Draft
1
[Hexagon] Remove post-decoding instruction adjustments
#156359 opened Sep 1, 2025 by s-barannikov • Draft
1
[TableGen][Decoder] Decode operands with zero width or all bits known backend:AArch64 backend:AMDGPU backend:ARM backend:CSKY backend:Hexagon backend:m68k backend:MIPS backend:PowerPC backend:RISC-V backend:Sparc tablegen
#156358 opened Sep 1, 2025 by s-barannikov Loading…
12
[Remarks] Remove redundant size from StringRefs (NFC)
#156357 opened Sep 1, 2025 by tobias-stadler Loading…
1
[CIR] Upstream FPToFPBuiltin ACosOp clang Clang issues not falling into any other category ClangIR Anything related to the ClangIR project
#156356 opened Sep 1, 2025 by AmrDeveloper Loading…
1
[mlir][ptr] Add translations to LLVMIR for ptr ops. mlir:llvm mlir
#156355 opened Sep 1, 2025 by fabianmcg Loading…
9
[lld][ELF] Improve the vulnerability in Orphan Sections initialization lld:ELF lld
#156354 opened Sep 1, 2025 by mykouHW Loading…
3
[lld][ELF] Enable link script to support absolute path matching lld:ELF lld
#156353 opened Sep 1, 2025 by mykouHW Loading…
2
[libc++] Simplify <tuple> further
#156351 opened Sep 1, 2025 by philnik777 • Draft
[clang][analyzer] Remove checker 'alpha.core.CastSize' clang:static analyzer clang Clang issues not falling into any other category
#156350 opened Sep 1, 2025 by balazske Loading…
3
[X86] X86TargetLowering::computeKnownBitsForTargetNode - add X86ISD::VPMADD52L\H handling backend:X86
#156349 opened Sep 1, 2025 by houngkoungting Loading…
1
10
[MLIR][NVVM] Update TMA Load Op mlir:gpu mlir:llvm mlir
#156347 opened Sep 1, 2025 by durga4github Loading…
7
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