Lowrisc with dual Rocket/Ariane support and X-windows

Taking into account all the SystemVerilog programmers out there, it was inevitable there would be a demand for a SystemVerilog version of LowRISC. This is a transitional release supporting both Rocket (from UC Berkley) and Ariane (from ETHZ). Supported boards are nexys4_ddr and GenesysII. In conjunction with an external VGA monitor and PMOD-BT adapter, both boards support X-Windows with Bluetooth mouse and keyboard. In addition, the GenesysII board supports 1000BaseT Ethernet and 1GByte of RAM available to Linux.

Binaries for refresh-v0.6 release

To be used in conjunction with lowrisc-quickstart repository and instructions on www.lowrisc.org

Refresh-v0.6 release candidate 3

Update Rocket to Mar 2018 vintage, Support bare-metal gdb debugging over USB-JTAG, support access to Debian-rv64GC, update to recent kernel, double speed to 50MHz, add 8-packet Ethernet buffer, support DHCP in boot loader and 10X speedup, widen I/O bus to 64-bits, incorporate UART TX/RX fifos, support colour console with keyboard up/down code PC compatibility.

Ethernet lowrisc release

These are the pre-built executables to go with the ethernet release of the lowrisc release for the Nexys4-DDR FPGA board. It provides access to networking, remote login via ssh, compilation locally via the riscv-poky distribution, as well as improved performance with a rewritten SD-card Verilog interface and Linux driver. Remote booting and Network filing system root is offered as well as standalone use with VGA screen and USB keyboard. Admittedly performance is modest relative to a modern workstation, however many areas of optimisation are possible before commiting to a chip.

Minion-v0.4 pre-release binaries for updating documentation

This is the release candidate code freeze for minion-v0.4. Use at your own risk.

lowRISC Debug Release

This is the lowRISC release v0.3, which mainly introduces the debug infrastructure. You can find a tutorial for the release here.

We use this release on Github to provide you prebuilt FPGA bitstreams and Linux. Please refer to the tutorial how to use them.

• boot.bin The boot image including bbl, vmlinux and init ramdisk.
• nexys4ddr_bram_boot.riscv The BRAM image to load boot.bin from SD to DDR.
• nexys4ddr_bram_jump.riscv The BRAM image to directly jump to DDR.
• nexys4ddr_fpga_debug.bit The FPGA bitstream with a trace debugger.
• nexys4ddr_fpga_standalone.bit The FPGA bitstream without a trace debugger.