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1. lowrisc-chip lowrisc-chip Public

   Forked from lowRISC/lowrisc-chip

   The root repo for lowRISC project and FPGA demos.

   SystemVerilog 1

2. picorv32 picorv32 Public

   Forked from YosysHQ/picorv32

   PicoRV32 - A Size-Optimized RISC-V CPU

   Verilog 1

3. vunit vunit Public

   Forked from VUnit/vunit

   VUnit is a unit testing framework for VHDL/SystemVerilog

   VHDL 1

4. riscv riscv Public

   Forked from openhwgroup/cv32e40p

   RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU

   SystemVerilog 1

5. zero-riscy zero-riscy Public

   Forked from lowRISC/ibex

   SystemVerilog 1 2

6. riscv-dbg riscv-dbg Public

   Forked from pulp-platform/riscv-dbg

   RISC-V Debug Support for our PULP Cores

   SystemVerilog 1