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The typical use case I have for this are boards where the USB function is provided using soft core. But having the user deal with that is often annoying when all they want is data in/out.
So typically I would like to have a platform that exposes for instances "uart_tx" and "uart_rx" or "in_data / in_valid / in_ready" as Resources just like if they were physical pins, but in fact they're just internal connections to a module that's always included when using that Platform.
In this particular case this module is written in Verilog and includes the SoC and USB core that handles all the USB and DFU etc ... and just provide an easy data pipe in/out.
The text was updated successfully, but these errors were encountered:
The typical use case I have for this are boards where the USB function is provided using soft core. But having the user deal with that is often annoying when all they want is data in/out.
So typically I would like to have a platform that exposes for instances "uart_tx" and "uart_rx" or "in_data / in_valid / in_ready" as Resources just like if they were physical pins, but in fact they're just internal connections to a module that's always included when using that Platform.
In this particular case this module is written in Verilog and includes the SoC and USB core that handles all the USB and DFU etc ... and just provide an easy data pipe in/out.
The text was updated successfully, but these errors were encountered: