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Issues: m-labs/nmigen

IO Buffer Instantiation Override
#110 by peteut was closed Jun 28, 2019
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33 Open 212 Closed
33 Open 212 Closed
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Issues list

For loops in Nmigen
#350 opened Sep 4, 2022 by ParasVekariya
No clk being generated
#349 opened Dec 30, 2021 by mayank-kabra2001
Want to know some details of the back
#346 opened May 27, 2021 by ekikun
1
Improve readability of assignments and add contexts for clock domains
#345 opened Apr 5, 2021 by ildus
Signal decoder inference for Enums doesn't work for Layout members
#333 opened May 26, 2020 by shawnanastasio
lambdasoc analysis & synthesis got error on intel platform.
#331 opened May 21, 2020 by franz-git
Generating async negedge reset
#329 opened May 15, 2020 by tariqafzal
Hierarchical Redundancy in emitted Verilog
#328 opened May 6, 2020 by BracketMaster
1
Installation fails if wheel not installed
#323 opened Apr 3, 2020 by alanvgreen
3
hdl.ast.Value.word_select() works incorrectly on actual platform (ECP5 Versa) bug
#310 opened Jan 23, 2020 by ghost
5
Support Platforms that include an existing design and expose interface to that design as Resource feature
#308 opened Jan 19, 2020 by smunaut
Add EnableSignal, useful for making Instances compatible with EnableInserter feature
#285 opened Dec 25, 2019 by Fatsie 0.2
21
Find solution to translate values to strings for Symbiyosys vcd files improvement upstream
#254 opened Oct 14, 2019 by RobertBaruch
19
Windows Batch is horrible; PowerShell is nicer improvement
#252 opened Oct 13, 2019 by emilazy
1
A tutorial improvement
#247 opened Oct 12, 2019 by RobertBaruch
2
Reliable installation on Windows improvement
#244 opened Oct 3, 2019 by whitequark
Specifying logical signal direction for ports of an elaboratable feature
#243 opened Sep 30, 2019 by Ravenslofty
1
Reconsider simulator interface backend:simulator improvement
#228 opened Sep 23, 2019 by whitequark 0.2
42
Memory with async read ports can synthesize to a BRAM on Xilinx platforms improvement platform:xilinx-7series platform:xilinx-spartan-3/6
#218 opened Sep 20, 2019 by whitequark
r_data is undefined after a simultaneous write to an empty AsyncFIFO bug platform:all
#217 opened Sep 20, 2019 by whitequark
1
Memory port transparency model is flawed bug upstream
#216 opened Sep 20, 2019 by whitequark
6
flow graph analysis and automation feature
#213 opened Sep 20, 2019 by jordens
13
Enhancing the FSM sub-language improvement
#206 opened Sep 14, 2019 by whitequark
12
ASIC support tracking issue improvement
#184 opened Aug 22, 2019 by whitequark
1 of 4 tasks
3
Reconsidering AsyncFIFO and resets improvement
#180 opened Aug 22, 2019 by whitequark
7
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