[RISCV] Support encoding cv32e40p SIMD instructions (plctlab#27)

Spec: https://github.com/openhwgroup/cv32e40p/blob/2a12206f84f53d4538d3876a1da367664c70e501/docs/source/instruction_set_extensions.rst. Co-authored-by: melonedo <[email protected]> Co-authored-by: liaochunyu <[email protected]>
melonedo · Feb 17, 2023 · b18cb93 · b18cb93
1 parent d549ffb
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diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -465,6 +465,17 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
         return Result;
       }
     }
+
+    if (STI.getFeatureBits()[RISCV::FeatureExtXcvsimd]) {
+      LLVM_DEBUG(dbgs() << "Trying CoreV SIMD custom opcode table:\n");
+      Result =
+          decodeInstruction(DecoderTableCoreVSIMD32, MI, Insn, Address, this, STI);
+      if (Result != MCDisassembler::Fail) {
+        Size = 4;
+        return Result;
+      }
+    }
+
     LLVM_DEBUG(dbgs() << "Trying RISCV32 table :\n");
     Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
     Size = 4;

diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
@@ -439,6 +439,15 @@ def HasExtXCoreVAlu
     : Predicate<"Subtarget->hasExtXCoreVAlu()">,
                AssemblerPredicate<(any_of FeatureExtXCoreVAlu),
                "'Xcorevalu' (ALU Operations)">;
+
+def FeatureExtXcvsimd
+    : SubtargetFeature<"xcvsimd", "HasExtXcvsimd", "true",
+                       "'Xcvsimd' (SIMD ALU)">;
+def HasExtXcvsimd
+    : Predicate<"Subtarget->hasExtXcvsimd()">,
+               AssemblerPredicate<(any_of FeatureExtXcvsimd),
+               "'Xcvsimd' (SIMD ALU)">;
+
 // CORE-V Load-Store Extension
 def FeatureExtXCoreVMem
     : SubtargetFeature<"xcorevmem", "HasExtXCoreVMem", "true",
@@ -452,7 +461,8 @@ def FeatureExtXCoreV
     : SubtargetFeature<"xcorev", "HasExtXCoreV", "true",
                        "'Xcorev' (CORE-V extensions)",
                        [FeatureExtXCoreVHwlp, FeatureExtXCoreVMac,
-                        FeatureExtXCoreVAlu, FeatureExtXCoreVMem]>;
+                        FeatureExtXCoreVAlu, FeatureExtXcvsimd, 
+                        FeatureExtXCoreVMem]>;
 def HasExtXCoreV : Predicate<"Subtarget->hasExtXCoreV()">,
                               AssemblerPredicate<(all_of FeatureExtXCoreV),
                               "'Xcorev' (CORE-V extensions)">;

diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsCOREV.td b/llvm/lib/Target/RISCV/RISCVInstrFormatsCOREV.td
@@ -281,3 +281,57 @@ class RVInstStore_rr<bits<3> funct3, bits<7> funct7, dag outs, dag ins,
   let Inst{11-7} = rs3;
   let Opcode = OPC_CUSTOM1.Value;
 }
+
+
+class CVInstSIMDRR<bits<5> funct5, bit F, bit funct1, bits<3> funct3, RISCVOpcode opcode, dag outs,
+              dag ins, string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+  bits<5> rs2;
+  bits<5> rs1;
+  bits<5> rd;
+
+  let Inst{31-27} = funct5;
+  let Inst{26} = F;
+  let Inst{25} = funct1;
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Opcode = opcode.Value;
+  let DecoderNamespace = "CoreVSIMD";
+}
+
+class CVInstSIMDR<bits<5> funct5, bit F, bit funct1, bits<3> funct3, RISCVOpcode opcode, dag outs,
+              dag ins, string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+  bits<5> rs1;
+  bits<5> rd;
+
+  let Inst{31-27} = funct5;
+  let Inst{26} = F;
+  let Inst{25} = funct1;
+  let Inst{24-20} = 0;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Opcode = opcode.Value;
+  let DecoderNamespace = "CoreVSIMD";
+}
+
+class CVInstSIMDRI<bits<5> funct5, bit F, bits<3> funct3, RISCVOpcode opcode, dag outs,
+              dag ins, string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+  bits<6> imm6;
+  bits<5> rs1;
+  bits<5> rd;
+
+  let Inst{31-27} = funct5;
+  let Inst{26} = F;
+  let Inst{25} = imm6{0}; // funct1 unused
+  let Inst{24-20} = imm6{5-1};
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Opcode = opcode.Value;
+  let DecoderNamespace = "CoreVSIMD";
+}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoCOREV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoCOREV.td
@@ -133,6 +133,142 @@ let Predicates = [HasExtXCoreVMac], hasSideEffects = 0, mayLoad = 0, mayStore =
                     Sched<[]>;
 } // Predicates = [HasExtXCoreVMac], hasSideEffects = 0, mayLoad = 0, mayStore = 0, Constraints = "$rd = $rd_wb"
 
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class CVSIMDALUrr<bits<5> funct5, bit F, bit funct1, bits<3> funct3, string opcodestr>
+    : CVInstSIMDRR<funct5, F, funct1, funct3, OPC_CUSTOM3, (outs GPR:$rd),
+              (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2"> {
+}
+
+class CVSIMDALUri<bits<5> funct5, bit F, bits<3> funct3, string opcodestr>
+    : CVInstSIMDRI<funct5, F, funct3, OPC_CUSTOM3, (outs GPR:$rd),
+              (ins GPR:$rs1, simm6:$imm6), opcodestr, "$rd, $rs1, $imm6"> {
+}
+
+class CVSIMDALUru<bits<5> funct5, bit F, bits<3> funct3, string opcodestr>
+    : CVSIMDALUri<funct5, F, funct3, opcodestr>;
+
+class CVSIMDALUr<bits<5> funct5, bit F, bit funct1, bits<3> funct3, string opcodestr>
+    : CVInstSIMDR<funct5, F, funct1, funct3, OPC_CUSTOM3, (outs GPR:$rd),
+              (ins GPR:$rs1), opcodestr, "$rd, $rs1"> {
+}
+
+multiclass CVSIMDBinarySigned<bits<5> funct5, bit F, bit funct1, string mnemonic> {
+  def CV_ # NAME # _H : CVSIMDALUrr<funct5, F, funct1, 0b000, "cv." # mnemonic # ".h">;
+  def CV_ # NAME # _B : CVSIMDALUrr<funct5, F, funct1, 0b001, "cv." # mnemonic # ".b">;
+  def CV_ # NAME # _SC_H : CVSIMDALUrr<funct5, F, funct1, 0b100, "cv." # mnemonic # ".sc.h">;
+  def CV_ # NAME # _SC_B : CVSIMDALUrr<funct5, F, funct1, 0b101, "cv." # mnemonic # ".sc.b">;
+  def CV_ # NAME # _SCI_H : CVSIMDALUri<funct5, F, 0b110, "cv." # mnemonic # ".sci.h">;
+  def CV_ # NAME # _SCI_B : CVSIMDALUri<funct5, F, 0b111, "cv." # mnemonic # ".sci.b">;
+}
+
+multiclass CVSIMDBinaryUnsigned<bits<5> funct5, bit F, bit funct1, string mnemonic> {
+  def CV_ # NAME # _H : CVSIMDALUrr<funct5, F, funct1, 0b000, "cv." # mnemonic # ".h">;
+  def CV_ # NAME # _B : CVSIMDALUrr<funct5, F, funct1, 0b001, "cv." # mnemonic # ".b">;
+  def CV_ # NAME # _SC_H : CVSIMDALUrr<funct5, F, funct1, 0b100, "cv." # mnemonic # ".sc.h">;
+  def CV_ # NAME # _SC_B : CVSIMDALUrr<funct5, F, funct1, 0b101, "cv." # mnemonic # ".sc.b">;
+  def CV_ # NAME # _SCI_H : CVSIMDALUru<funct5, F, 0b110, "cv." # mnemonic # ".sci.h">;
+  def CV_ # NAME # _SCI_B : CVSIMDALUru<funct5, F, 0b111, "cv." # mnemonic # ".sci.b">;
+}
+
+
+let Predicates = [HasExtXcvsimd], hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+  defm ADD :    CVSIMDBinarySigned<0b00000, 0, 0, "add">;
+  defm SUB :    CVSIMDBinarySigned<0b00001, 0, 0, "sub">;
+  defm AVG :    CVSIMDBinarySigned<0b00010, 0, 0, "avg">;
+  defm AVGU :   CVSIMDBinarySigned<0b00011, 0, 0, "avgu">;
+  defm MIN :    CVSIMDBinarySigned<0b00100, 0, 0, "min">;
+  defm MINU : CVSIMDBinaryUnsigned<0b00101, 0, 0, "minu">;
+  defm MAX :    CVSIMDBinarySigned<0b00110, 0, 0, "max">;
+  defm MAXU : CVSIMDBinaryUnsigned<0b00111, 0, 0, "maxu">;
+  defm SRL :  CVSIMDBinaryUnsigned<0b01000, 0, 0, "srl">;
+  defm SRA :  CVSIMDBinaryUnsigned<0b01001, 0, 0, "sra">;
+  defm SLL :  CVSIMDBinaryUnsigned<0b01010, 0, 0, "sll">;
+  defm OR :     CVSIMDBinarySigned<0b01011, 0, 0, "or">;
+  defm XOR :    CVSIMDBinarySigned<0b01100, 0, 0, "xor">;
+  defm AND :    CVSIMDBinarySigned<0b01101, 0, 0, "and">;
+
+  def CV_ABS_H :    CVSIMDALUr<0b01110, 0, 0, 0b000, "cv.abs.h">;
+  def CV_ABS_B :    CVSIMDALUr<0b01110, 0, 0, 0b001, "cv.abs.b">;
+
+  // 0b01111xx: UNDEF
+
+  defm DOTUP :   CVSIMDBinarySigned<0b10000, 0, 0, "dotup">;
+  defm DOTUSP :  CVSIMDBinarySigned<0b10001, 0, 0, "dotusp">;
+  defm DOTSP :   CVSIMDBinarySigned<0b10010, 0, 0, "dotsp">;
+  defm SDOTUP :  CVSIMDBinarySigned<0b10011, 0, 0, "sdotup">;
+  defm SDOTUSP : CVSIMDBinarySigned<0b10100, 0, 0, "sdotusp">;
+  defm SDOTSP :  CVSIMDBinarySigned<0b10101, 0, 0, "sdotsp">;
+
+  // 0b10110xx: UNDEF
+
+  def CV_EXTRACT_H :    CVSIMDALUri<0b10111, 0, 0b000, "cv.extract.h">;
+  def CV_EXTRACT_B :    CVSIMDALUri<0b10111, 0, 0b001, "cv.extract.b">;
+  def CV_EXTRACTU_H :   CVSIMDALUri<0b10111, 0, 0b010, "cv.extractu.h">;
+  def CV_EXTRACTU_B :   CVSIMDALUri<0b10111, 0, 0b011, "cv.extractu.b">;
+  def CV_INSERT_H :   CVSIMDALUri<0b10111, 0, 0b100, "cv.insert.h">;
+  def CV_INSERT_B :   CVSIMDALUri<0b10111, 0, 0b101, "cv.insert.b">;
+
+  def CV_SHUFFLE_H :    CVSIMDALUrr<0b11000, 0, 0, 0b000, "cv.shuffle.h">;
+  def CV_SHUFFLE_B :    CVSIMDALUrr<0b11000, 0, 0, 0b001, "cv.shuffle.b">;
+  def CV_SHUFFLE_SCI_H : CVSIMDALUri<0b11000, 0, 0b110, "cv.shuffle.sci.h">;
+  def CV_SHUFFLEI0_SCI_B : CVSIMDALUri<0b11000, 0, 0b111, "cv.shuffleI0.sci.b">;
+
+  def CV_SHUFFLEI1_SCI_B : CVSIMDALUri<0b11001, 0, 0b111, "cv.shuffleI1.sci.b">;
+
+  def CV_SHUFFLEI2_SCI_B : CVSIMDALUri<0b11010, 0, 0b111, "cv.shuffleI2.sci.b">;
+
+  def CV_SHUFFLEI3_SCI_B : CVSIMDALUri<0b11011, 0, 0b111, "cv.shuffleI3.sci.b">;
+
+  def CV_SHUFFLE2_H :    CVSIMDALUrr<0b11100, 0, 0, 0b000, "cv.shuffle2.h">;
+  def CV_SHUFFLE2_B :    CVSIMDALUrr<0b11100, 0, 0, 0b001, "cv.shuffle2.b">;
+
+  // 0b11101xx: UNDEF
+
+  def CV_PACK :      CVSIMDALUrr<0b11110, 0, 0, 0b000, "cv.pack">;
+  def CV_PACK_H :    CVSIMDALUrr<0b11110, 0, 1, 0b000, "cv.pack.h">;
+
+  def CV_PACKHI_B :    CVSIMDALUrr<0b11111, 0, 1, 0b001, "cv.packhi.b">;
+  def CV_PACKLO_B :    CVSIMDALUrr<0b11111, 0, 0, 0b001, "cv.packlo.b">;
+
+  defm CMPEQ : CVSIMDBinarySigned<0b00000, 1, 0, "cmpeq">;
+  defm CMPNE :  CVSIMDBinarySigned<0b00001, 1, 0, "cmpne">;
+  defm CMPGT :  CVSIMDBinarySigned<0b00010, 1, 0, "cmpgt">;
+  defm CMPGE :  CVSIMDBinarySigned<0b00011, 1, 0, "cmpge">;
+  defm CMPLT :  CVSIMDBinarySigned<0b00100, 1, 0, "cmplt">;
+  defm CMPLE :  CVSIMDBinarySigned<0b00101, 1, 0, "cmple">;
+  defm CMPGTU : CVSIMDBinarySigned<0b00110, 1, 0, "cmpgtu">;
+  defm CMPGEU : CVSIMDBinarySigned<0b00111, 1, 0, "cmpgeu">;
+  defm CMPLTU : CVSIMDBinarySigned<0b01000, 1, 0, "cmpltu">;
+  defm CMPLEU : CVSIMDBinarySigned<0b01001, 1, 0, "cmpleu">;
+
+  def CV_CPLXMUL_R :    CVSIMDALUrr<0b01010, 1, 0, 0b000, "cv.cplxmul.r">;
+  def CV_CPLXMUL_I :    CVSIMDALUrr<0b01010, 1, 1, 0b000, "cv.cplxmul.i">;
+  def CV_CPLXMUL_R_DIV2 :    CVSIMDALUrr<0b01010, 1, 0, 0b010, "cv.cplxmul.r.div2">;
+  def CV_CPLXMUL_I_DIV2 :    CVSIMDALUrr<0b01010, 1, 1, 0b010, "cv.cplxmul.i.div2">;
+  def CV_CPLXMUL_R_DIV4 :    CVSIMDALUrr<0b01010, 1, 0, 0b100, "cv.cplxmul.r.div4">;
+  def CV_CPLXMUL_I_DIV4 :    CVSIMDALUrr<0b01010, 1, 1, 0b100, "cv.cplxmul.i.div4">; 
+  def CV_CPLXMUL_R_DIV8 :    CVSIMDALUrr<0b01010, 1, 0, 0b110, "cv.cplxmul.r.div8">;
+  def CV_CPLXMUL_I_DIV8 :    CVSIMDALUrr<0b01010, 1, 1, 0b110, "cv.cplxmul.i.div8">;
+
+  def CV_CPLXCONJ :    CVSIMDALUr<0b01011, 1, 0, 0b000, "cv.cplxconj">;
+
+  // 0b01011xx: UNDEF
+
+  def CV_SUBROTMJ :    CVSIMDALUrr<0b01100, 1, 0, 0b000, "cv.subrotmj">;
+  def CV_SUBROTMJ_DIV2 :    CVSIMDALUrr<0b01100, 1, 0, 0b010, "cv.subrotmj.div2">;
+  def CV_SUBROTMJ_DIV4 :    CVSIMDALUrr<0b01100, 1, 0, 0b100, "cv.subrotmj.div4">; 
+  def CV_SUBROTMJ_DIV8 :    CVSIMDALUrr<0b01100, 1, 0, 0b110, "cv.subrotmj.div8">;  
+
+  def CV_ADD_DIV2 :    CVSIMDALUrr<0b01101, 1, 0, 0b010, "cv.add.div2">;
+  def CV_ADD_DIV4 :    CVSIMDALUrr<0b01101, 1, 0, 0b100, "cv.add.div4">;
+  def CV_ADD_DIV8 :    CVSIMDALUrr<0b01101, 1, 0, 0b110, "cv.add.div8">;
+
+  def CV_SUB_DIV2 :    CVSIMDALUrr<0b01110, 1, 0, 0b010, "cv.sub.div2">;
+  def CV_SUB_DIV4 :    CVSIMDALUrr<0b01110, 1, 0, 0b100, "cv.sub.div4">;
+  def CV_SUB_DIV8 :    CVSIMDALUrr<0b01110, 1, 0, 0b110, "cv.sub.div8">; 
+}
+
 let Predicates = [HasExtXCoreVMac], hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
   // Signed 16x16 bit muls
   def CV_MULS     : RVInstMac16<0b10, 0b000, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),

diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -99,6 +99,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
   bool HasExtXCoreVMac = false;
   bool HasExtXCoreVAlu = false;
   bool HasExtXCoreVMem = false;
+  bool HasExtXcvsimd = false;
   bool HasRV64 = false;
   bool IsRV32E = false;
   bool EnableLinkerRelax = false;
@@ -205,6 +206,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
   bool hasExtXCoreVMac() const { return HasExtXCoreVMac; }
   bool hasExtXCoreVAlu() const { return HasExtXCoreVAlu; }
   bool hasExtXCoreVMem() const { return HasExtXCoreVMem; }
+  bool hasExtXcvsimd() const { return HasExtXcvsimd; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return IsRV32E; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }